Last June, IBM announced that a team of engineers had made test circuits exhibiting a rate of electron mobility approximately 80% higher than in standard silicon-based technology. Successful use of strained silicon has the potential to improve IC speeds by up to 35% and greatly reduce power consumption, IBM says.

More recently, AmberWave in March signed a partnership agreement with IQE Silicon Compounds for high-volume production of 200-mm epitaxial wafers based on AmberWave's strained-silicon technology. Based in Cardiff, Wales, IQE is a global supplier of outsourced epi wafers. The partners claim their pact tackles another important challenge: the need to slash capital expenditures in the era of the billion-dollar IC factory. The technology makes use of existing fabs and silicon processes.

NO SHRINK: A CMOS transistor sits atop strained SiGe film in this AmberWave schematic. Image is not shown to scale. SCHEMATIC COURTESY OF AMBERWAVE SYSTEMS; ILLUSTRATION BY JAMES SCHLESINGER

The semiconductor R&D community has striven for more than 15 years to develop strained silicon as a cost-effective manufacturing alternative to the tyranny imposed by the need to continually reduce chip geometries every 18 months. Rather than shrinking the size of the transistor, strained-silicon technology changes the nature of the wafer itself by slightly stretching the placement of the atoms. This lessens resistance, permitting electrons to travel faster.

NO STRAIN: IBM image shows electrons flowing through strained silicon. Electrons move up to 70% faster than normal because of less resistance. IMAGE COURTESY OF IBM

While both IBM and AmberWave deposit layers of silicon germanium through CVD to stretch the crystal lattice, the latter company says it uses a proprietary method that avoids a surface defect problem called crosshatch. Gene Fitzgerald, cofounder with Mayank Bulsara of the 35-employee firm, developed the technique at MIT. The ability to neutralize the crosshatch problem enables AmberWave to deposit up to 100% germanium. IBM can use only a 15% germanium concentration, according to the start-up.

AmberWave's sequential CMP-epitaxial process does not create additional defects, Bulsara says. "We have a patented process where we planarize the surface so that we have a very smooth strained-silicon film that doesn't create any problems with lithography when you're making circuits."

In developing the technology with Fitzgerald as his graduate advisor at MIT, Bulsara says they used a Strasbaugh CMP system. "We have found it to be completely compatible in terms of working with commercial CMP suppliers. We've qualified several suppliers. The slurries, even the consumables, are the same."

Nevertheless, there are some challenges, he notes. In particular, the use of germanium "creates a different removal rate," one that is slower by a factor of at least two. The "different behavior" of germanium means that normal optical metrology is ineffective for film inspection.

Robert Harper, technical sales manager for IQE Silicon Compounds, agrees that volume production of strained-silicon wafers will push the limits of conventional metrology. "The process control for this technology is challenging, but more with respect to the complexity of the metrology requirements than with the repeatability of the results we're achieving to date."

Harper says transmission electron microscopes and related high-end measurement systems are needed, analytical equipment he calls "not typical fab tools." Some fabs carry atomic-force microscopes, which also are needed, but he emphasizes that these requirements "add to the entry cost for anyone considering growing strained-silicon layers themselves.

"One of the challenges is that some of the metrology tests are destructive," he continues, "and so we are looking at alternative nondestructive methods, such as grazing x-ray, to replace cross-sectional TEM, for example. We would also like to bring as many measurements as possible into our production line, since we need the benefit of real-time feedback." He says cross-sectional TEM can take two days for sample preparation and measurement.

Using SIMS to control and measure the germanium fraction "through the grade and constant-composition layer is one of the more challenging aspects of process control," Harper emphasizes, "because the growth rate increases for higher-fraction germanium layers."

The IBM team, which has produced strained-silicon MOSFET devices, has noted that strained-silicon technology faces three key challenges: short channel effect, silicon dislocations, and keeping the strain level during manufacturing. Big Blue claims that its expertise in both silicon germanium and SOI technologies gives it a strong grounding and the clout to wrestle with process. Basically, the largest cost comes from perfecting material deposition and perfecting yields.

"Intrinsically, strained-silicon technology does not have any known yield-limiting issues," asserts Bulsara.

AmberWave says previous research has focused primarily on NMOS devices for the ease of electron mobility. However, the start-up has demonstrated current improvements of more than 40% in PMOSFETs. Calling it revolutionary, the company says the advance would permit fabrication of strained-silicon circuits with symmetric NMOS and PMOS drive-current improvements. It's another step along the path to vast improvements in silicon CMOS performance to heed the call for the high-mobility materials cited in the International Technology Roadmap for Semiconductors at the 100-nm technology node and lower, AmberWave points out.

According to one news report, IBM ultimately may build dual-gate devices by combining strained silicon with an SOI substrate in an attempt to overcome difficult performance problems with CMOS scaling. AmberWave says that its licensed Generation 1 strained-silicon technology will enable IQE Silicon Compounds to offer the start-up's base of licensees around the world immediate access to 200-mm wafers.

Harper says the company has developed a process for its current 200-mm tool platforms and is considering other tools for both 200- and 300-mm wafers. "Volume production of low-defect wafers is on the way, and we expect to be shipping thousands of wafers in our first project phase."