As the semiconductor industry has continued to advance in accordance with Moore's law, more cleaning steps have been added to the fabrication process to ensure that critical dimensions will not be compromised by contaminants. Depending on the device design and the number of interconnect layers, a wafer may undergo many clean steps during FEOL and BEOL processing.¹ In addition, cleaning processes must not only strip resist from the wafer surface, but must also remove complex postetch residue and other contaminants, such as mobile metal ions and particles, which has created a need for increasingly sophisticated cleaning chemistries. At the same time, it is essential that these chemistries be compatible with such new materials as copper and low-k dielectrics.

Although batch cleaning methods have been used successfully for years, single-wafer processing has been gaining support.² Cleaning wafers individually may offer more opportunity to control the process and improve uniformity both across the wafer and from wafer to wafer, thereby improving yield. Currently, the drawbacks to such processing are its relatively low throughput and high cost.

In order to be competitive with batch systems, which have a typical throughput of approximately 200 wafers per hour, a single-wafer process would need to be capable of cleaning and rinsing a wafer in 1 minute or less at room temperature. The development of new cleaning chemistries will be essential to achieve that goal.

While striving to meet the challenges of advanced device technologies, wafer fabs are also devoting significant efforts to conserving resources and complying with environmental, health, and safety requirements. Wet cleans, wet etches, and subsequent rinse steps use a significant percentage of the chemicals and water utilized in wafer production.³ The development of new cleaning chemistries and optimized postclean treatments presents opportunities to significantly reduce current consumption levels while ensuring operator safety. Innovative formulations also may enable fabs to manage spent product better by adopting new reclaim, reuse, and disposal methods that meet all legal requirements and fulfill social responsibilities.

Finally, a continuing concern of the industry is the cost of performance improvements. New products and processes must address the need to hold down their users' cost of ownership (COO). The development of the cleaning technologies presented in this article is being driven by a desire to assist the industry in all of these areas.

Advanced Hydroxylamine Cleaning Technologies

Since introducing the first hydroxylamine-based cleaning chemistry, EKC Technology (Hayward, CA) has developed several such formulations that have proven effective in the postetch cleaning of such conventional interconnect structures as aluminum lines and pads, oxide vias and contacts, and poly gates, with minimal metal corrosion. The formulations also are effective in oxide etch.⁴ Suited for use in both immersion baths and spray tools, these chemistries typically have a long bath life (15 to 45 minutes) and a wide process window (55° to 85°C).

One recently formulated chemistry was optimized to reduce COO by utilizing hydroxylamine more efficiently, yet maintain the process window and bath-life advantages of its predecessors. In-house testing established its compatibility with aluminum, titanium, and tungsten, as well as TEOS. As shown in Figure 1, the titanium etch rate of the new formulation was significantly lower than that of a conventional chemistry, while the aluminum and oxide compatibility of the two chemistries was comparable.

Figure 1: Comparative etch rates on titanium, aluminum, tungsten, and TEOS for a conventional cleaning chemistry and a new optimized formulation.

The scanning electron microscope (SEM) images in Figure 2 indicate that the new formulation cleans oxide via structures effectively. The cleaning used in the experiment that produced these images took 20 minutes and included an isopropyl alcohol rinse; cleaning temperature was 75°C.

Semiaqueous Cleaning Chemistries

An alternative approach to wet cleaning, semiaqueous chemistries have been designed for use with single-wafer processing equipment as well as with wet-bench and spray batch tools. Composed of organic solvents, water, low concentrations of active species, and buffering agents to control chemical activity, they typically have a pH range of 8–10. Most commercially available semiaqueous products can be used at near-ambient temperatures (23°–30°C) with process times varying between 2 and 30 minutes. In addition, they can be rinsed directly in water, reducing water-rinse volumes.^5–7 Semiaqueous products exhibit good cleaning ability on metal (including copper) and oxide via structures, and are compatible with many new low-k materials and unlanded metal lines on tungsten plugs. The cleaning performance of one semiaqueous chemistry on oxide structures with a 5-minute process time at 23°C is demonstrated in Figure 3.

Wet-chemical cleaning processes for postetch residue removal typically involve two separate steps—cleaning and rinsing. During the cleaning step, an active chemical ingredient is used to dissolve the residue, and the rinsing step carries away both the cleaning chemical and reaction by-products. With traditional amine-based chemistries, dissolution proceeds from the outer surface of a structure inward to its walls. For these systems, an intermediate alcohol rinse may be employed to prevent the accumulation of high concentrations of hydroxide ions in the final rinsewater.

In contrast, semiaqueous chemistries clean by a diffusion process. The active species in the cleaning chemistry diffuses into the postetch residue, which is converted into smaller subspecies. Only a small fraction of this converted material is dissolved. Most remains in place until the DI-water rinse step.^8,9 As this residue layer builds up, the conversion reaction slows down, which could lead to extended process times. However, the use of an aqueous spray rinse between two separate chemical dispense steps can minimize overall chemical exposure time while efficiently removing cleaning by-products.^9–11

Because of their low active-ingredient and water content, it is important that semiaqueous chemistries maintain their compositional and pH levels during a typical bath life. Low concentrations of water-soluble amine species tend to act as pH buffering agents, as shown below:

HR₃N⁺ + OH^– ↔ R₃N + H₂O

which results in semiaqueous chemistries with pH values between 8.5 and 9.5. The industry has seen formulations in which these values may shift as much as 4–5 pH units toward the acid side during bath life or when diluted with water, affecting the reaction kinetics and creating the potential for corrosion problems. But such shifts can be prevented by including the proper solvents and buffering agents in the chemistry formulation. Figure 4 shows the stability of one semiaqueous chemistry with different DI-water dilutions.⁹

Figure 4: Stability of the pH level of a semiaqueous cleaning chemistry over time at different DI-water dilutions.

Since traditional amine-based chemistries operate by dissolving postetch residues, a layer of nitrogen or corrosion-inhibitor species may remain on the cleaned surfaces prior to rinsing.⁹ As the DI rinsewater diffuses through this organic film, the combination of amines and water can generate OH^– species that can shift the pH on metal surfaces to >11. Aluminum and even copper can be corroded in the presence of such a high pH value and an amine species.

This corrosion mechanism does not occur with semiaqueous chemistries. These formulations do not contain amines in sufficient quantities to form additional corrosive hydroxide species in the rinsewater and do not experience an increase in pH above their initial value. The pH may shift ~0.8–1 unit lower, but not more.

As materials such as copper and low-k dielectrics are introduced, a new class of chemistries may be able to provide a bridge between the cleaning processes used on current designs and those that will be required for succeeding generations of devices. One experimental chemistry, for example, requires few adjustments from typical current cleaning practices, performs comparably to conventional chemistries, and is compatible with copper and most low-k materials, as seen in Figure 5 and Table I. The SEM images in Figures 6, 7, and 8 show its effectiveness at cleaning metal lines, oxide via structures, and copper/TEOS structures for 15 minutes at 70°C, 20 minutes at 65°C, and 30 minutes at 65°C, respectively.

Figure 5: Comparative etch rates on various materials for a conventional cleaning chemistry and an experimental chemistry that was developed for use during the transition to copper and low-k dielectric interconnects.

Material Etch Rate(Å/min) Compatibility SiLK <1 Pass Coral <1 Pass Flare <1 Pass SiOC 1.9 Pass Thermal oxide <1 Pass TEOS 1.2 Pass Porous SiLK <1 Pass

Table I: Typical dielectric compatibility test results for the experimental chemistry.

Selecting Appropriate Metrics to Judge Cleaning Quality

Among the issues raised by the transition to copper and low-k dielectric materials is a need to change the metrics for gauging cleaning efficacy. As a result, the development of totally new cleaning chemistries for use with next-generation devices will need to follow a dramatically different path than has been taken previously.

From an R&D standpoint, formulating a cleaning chemistry to follow plasma etching has relied on SEM images. As a rule, a great deal of postetch residue is visible in a micrograph. To a lesser extent, the same is true for vias. Because via residue is more challenging to remove than metal residue, its production is undesirable. However, if the via etch process must punch through a titanium nitride capping layer, some visible residue will be formed. In both cases, there is an excellent correlation between residue removal performance, as judged by SEM inspection and by more-elaborate methods such as electrical testing.

This correlation does not apply in the case of copper interconnects, which include a barrier layer (commonly silicon nitride or a similar material) on top of the metal. This barrier is etched in order to open on the copper, and if a large amount of visible residue is formed during etching, its chemical nature will render it insoluble. Thus, it cannot be selectively removed without damaging either the native copper or the surrounding dielectric, or both. For this reason, optimized etch processes on copper interconnects typically do not reveal visible amounts of residue.

The lack of residue does not mean that there is no need for a postetch cleaning step. Even an optimized etch process will tend to backsputter copper onto the sidewalls of the dielectric. If it is not removed, this metal will ultimately become trapped inside the dielectric behind a subsequent barrier layer (normally tantalum or tantalum nitride), thereby compromising the electrical properties of the dielectric. In addition, having a cleaning step after barrier etch reduces the likelihood that there will be an excessively thick copper-oxide layer at the underlying copper surface. Although subsequent deposition processes are designed to remove such layers in situ, reliance on these processes in the absence of a cleaning step is probably risky.

The challenge for formulators of next-generation chemical cleans, therefore, lies in determining (and then utilizing) appropriate metrics to replace SEM for judging the quality of cleaning processes. Rudimentary screening techniques such as etch rates on blanket films of metals and dielectrics, which have been used for many years, will take on increased importance. The results of these types of tests must be treated with caution, however. The use of processes that simulate or duplicate etching conditions will be essential, given that most low-k films are more sensitive to both wet and dry chemistries than are silicon oxides.

The inadequacy of the SEM metric also means that formulators of new cleaning chemistries must collaborate with device manufacturers. For example, EKC Technology established such a relationship with CEA-LETI (Grenoble, France). Two cleaning chemistries designed specifically for copper integration have resulted from their collaborative work.^12,13

One chemistry was developed for post–Si₃N₄ etch opening to copper in the presence of a TEOS dielectric, and its adoption has made it possible to migrate from TEOS to SiLK. That chemistry's cleaning effectiveness, as compared with dilute hydrofluoric acid and DI water, is illustrated by the transmission electron microscope (TEM) images in Figures 9 and 10.

Figure 11 illustrates a copper and porous SiLK (v.7) structure constructed using the chemistry and associated electrical data illustrating the dependence of line resistance on etch and cleaning processes.¹⁴ Typical process conditions for this chemistry are 50°C for 10 to 20 minutes. It can be used in either immersion or spray batch cleaning platforms. Whether it is applicable to single-wafer systems as well remains unclear because of throughput concerns.

The other chemistry was developed for a specific cleaning application during buried hard-mask integration. Subsequent in-house testing suggests that it (or a variant thereof) may find widespread use in copper residue removal.

Other approaches may be reasonably pursued in the area of copper cleaning, including the use of semiaqueous chemistries for postetch residue removal. Several chemical suppliers offer products in this class, but there is growing concern that, depending on the choice of low-k dielectric, a fluoride-based cleaning mechanism may not be suitable for cleaning advanced devices that require stringent critical dimension control. Ultimately, the ability to control the selectivity of such cleaning chemistries will determine whether this concern can be overcome.

Finally, the expanded use of copper and low-k dielectrics (particularly dielectric materials with increasing porosity) may yet herald the return of wet photoresist removal to advanced semiconductor processing. In some cases, dry ashing has been found to damage the sensitive low-k materials required for next-generation devices. A compatible wet photoresist remover may provide a viable solution to this problem. The extent to which this approach is adopted will depend on which integration schemes and low-k materials become industry standards.

Conclusion

To date, the semiconductor industry has been successful in achieving the ever-increasing performance capabilities of IC devices. To continue this trend, it has been necessary to introduce new interconnect materials and processes that meet lower resistivity and dielectric-constant targets for improved data transmission. Modified processes and combinations of materials (e.g., copper, AlCu, and low-k and barrier/nucleation layers) have created numerous integration challenges, one of the most difficult of which is maintaining line and structure integrity during the numerous wafer-cleaning steps required to complete a typical integrated circuit. To meet this challenge, new approaches to chemical cleaning methods for the removal of photoresist, dry-etch residue, particles, and metal ion contaminants are continually being investigated. New and experimental chemistries must employ innovative chemical combinations developed specifically for current- and next-generation interconnect materials.

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References

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2. R DeJule, "A Move to Single Wafer Cleaning," Solid State Technology Web page exclusive [cited November 6, 2001]; available from Internet: www.solid-state.com.

3. TS Roche and TW Peterson, "Reducing DI Water Use," Solid State Technology Web page [cited December 1996]; available from Internet: www.solid-state.com.

4. EKC Technology technical data (Danville, CA: EKC Technology).

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11. J Rosato et al., "Studies of Rinse Efficiencies in Wet Cleaning Tools," in Proceedings of Cleaning Technology in Semiconductor Device Manufacturing (Pennington, NJ: Electrochemical Society, 1994), 140–152.

12. D Louis et al., "Improved Post Etch Cleaning for Low-k and Copper Integration for 0.18-µm Technology," Microelectronic Engineering 46, no 1 (1999): 307–310.

13. D Louis et al., "Post Etch Cleaning of Dual Damascene System Integrating Copper and SiLK, in Proceedings of the IEEE International Interconnect Technology Conference (Piscataway, NJ: IEEE, 1999), 103–105.

14. J Waeterloos et al., "Damascene Integration Feasibility of Developmental Porous SiLK Resin Film" (paper presented at the Advanced Metallization Conference, Montreal, Canada, October 9–10, 2000).

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