Behind the Mask

Implementing simulation-based mask-qualification technology

S. Y. Chiou, Henry Lei, W. J. Liu, and Daryl Chiang, UMC; and Linyong Pang, Jiunn-Hung Chen, and J. Tracy Weed, Numerical Technologies

Simulation-based mask qualification provides data on wafer CD, the impact of defects on linewidth control, the quality of mask repairs, and feature specs without having to print a wafer.

The pursuit of faster, more cost-effective and less power-hungry integrated circuits has placed a burden on semiconductor technology R&D, but it has created significant opportunities as well. Over the last two decades, optical microlithography in particular has made significant advances in the areas of illumination sources, lens and photoresist performance, and mask technology, and will be compelled to make even further leaps to meet the demands of the industry's latest technology roadmap.^1,2

While the stand-alone development of new technologies to solve complex problems is important, technological innovations also must be integrated into the workings of the fab. In the field of optical microlithography, overall process control must be enhanced to assure necessary pattern integrity. Nowhere is system integration, or the handoff between technology steps, more important than between the maskmaker and the mask user. In that area, radical measures are called for to achieve faster turnaround times and cost reductions.³

The exchange between maskmaker and mask user typically culminates in some level of mask qualification by the user. The qualification process can be viewed as a combination of indirect and direct procedures. Indirect procedures are based on specifications generated through industry consensus, internal company roadmaps, experiments, and experience. They also are based on the assumptions that parameters that must be controlled are known, that they are in fact controllable, that the target values are known, and that the effects of these parameters on the end result are clear. Because new requirements, processes, and definitions are being introduced continually, specifications must be reassessed to determine their continued applicability and to prevent them from being too detailed or too vague.⁴

Direct mask-qualification procedures begin when a fab receives a mask from the maskmaker. First, the fab performs some level of visual inspection by comparing the mask's values to set specifications or performs lithographic exposures and CD measurements of the resulting wafer images. The images are then compared to specifications set forth in the design and process documentation.

Although accepted as routine industry practices, visual and lithographic/CD inspections have many drawbacks: data are not always available to generate accurate and meaningful comparative specifications; industry consensus is not applicable to every company; the qualification procedures are cumbersome, time-consuming, and costly; and many of the procedural steps are redundant.

Advanced wafer fabs will be able to deliver the increasingly aggressive process technologies demanded by customers, while realizing time and cost reductions, only if the acceptance and qualification process becomes seamless, standardized, and automated. The demand for an automated photomask-qualification tool has increased significantly since the advent of subwavelength-based technologies.^5,6

This article discusses work performed at United Microelectronic Corp. (UMC) in Hsinchu, Taiwan, to improve maskmaker/fab qualification as part of an effort to achieve overall productivity goals. As a foundry, UMC must implement and monitor world-class processes at multiple sites. In conjunction with Numerical Technologies (San Jose), a pilot project has been established at UMC to develop a simulation-based mask defect-inspection infrastructure. Developing this infrastructure has involved evaluating the industry's ability to create simulation-based mask-qualification technology, giving industry organizations access to information obtained from the project, and implementing this technology on the fab floor.

Simulation-Based Photomask Qualification

As a means of bridging the gap between the maskmasker and mask user, UMC has defined a simulation-based mask-qualification approach. Using simulation-based photomask qualification, fab personnel can access data that are important to photomask acceptance without actually having to print a wafer. Such data include wafer CD, the impact of a given defect on linewidth control, the quality of repairs, and the degree to which a given feature meets specifications.

To conduct the simulation study, UMC used Numerical Technologies' Virtual Stepper, photomask-qualification software that performs simulations to determine what will be transferred to silicon under a certain set of processing conditions. Virtual Stepper employs an advanced simulation engine to emulate the optical system in a state-of-the-art stepper. It uses the reticle images produced by mask inspection or review systems as inputs and provides printed images from wafers as outputs. Multiple analysis options such as intensity plots, feature size versus exposure level, feature size versus defocus, and process latitude trade-off curves help quantify the results. The software's scripting capability allows users to introduce varying levels of automation in order to meet inspection and manufacturing process requirements.

Table I summarizes data related to the evaluation and application of this simulation technology, which has been used successfully to predict a wide range of defect types across multiple inspection wavelengths, technology nodes, pattern types, and inspection tools. Virtual Stepper simulations, simulation outputs from an AIMS aerial image measurement system (Carl Zeiss, Oberkochen, Germany), and actual wafer images have typically been compared and evaluated.

Technology Node Mask Type Fab or Mask House Stepper Wavelength Inspection Tool/ Wavelength Programmed Hard Defects 0.25 µm Binary AMD KrF 248 nm Zygo KMS400i/364 nm Isolated dot between lines with no assist bars7 0.18 µm Binary Sony KrF 248 nm KLAT365/364 nm Edge protrusion, intrusion, and repaired defects8,9 0.18 µm Binary Mask shop A KrF 248 nm Lasertec MD2000/364 nm Contact hole size 0.15 µm Binary Sony KrF 248 nm KLAT365/364 nm Edge protrusion, intrusion, and repaired defects8,9 0.15 µm Binary Mask shop A KrF 248 nm Lasertec MD2000/364 nm Contact hole size, protrusion, and intrusion on line/space 0.13 µm Binary AMD ArF 193 nm Zygo KMS450i/364 nm Protrusion and intrusion on dense line, pinhole on isolated line, and isolated line with scattering bars10,11 0.18 µm Attenuated Sony KrF 248 nm KLAT365 UVHR/364 nm Protrusion, intrusion, and isolated defect12 0.18 µm Attenuated Fab A KrF 248 nm SLF27/364 nm Protrusion and intrusion on isolated, dense, and intermediate contact holes 0.18 µm Attenuated Photronics KrF 248 nm KMS 400/364 nm Isolated dot on line/island feature13 0.18 µm Attenuated Photronics KrF 248 nm ETEC Aris2li/364 nm Dense contact hole, line space, and dense rectangle feature14 0.13 µm Attenuated Sony KrF 248 nm KLAT365 UVHR/364 nm Protrusion, intrusion, and isolated defect12 0.13 µm Attenuated Mask shop A KrF 248 nm KLAT365 UVHR/364 nm, Lasertec MD2000/364 nm Protrusion, intrusion, and isolated defect on contact hole and line/space

Table I: Summary data related to the evaluation and application of the simulation technology.

In a typical mask manufacturing process flow, the reticle is handed off to the wafer fab after a mask review. Mask houses can use simulation-based mask-qualification tools to review, inspect, and repair masks, while wafer fabs can use them to perform mask inspections, repair validations, and requalifications. At each of these steps, knowledge of the final wafer image is crucial for answering critical maskmaking questions: Is CD control within specifications? Will a particular defect print? Should that defect be repaired? Was the repair successful? How will the defect affect surrounding features? Or most importantly: Will the reticle perform as intended? Incorrect decisions at any point can increase mask cost and turnaround time.

Once the fab receives the photomask, it must perform defect analysis using the same steps and tools (incoming quality control, mask requalification) that the mask house used for outgoing quality control. This procedure ensures that there will be a common basis for communication between the maskmaker and mask user.

Experimental Methods

Two types of photomasks were used to evaluate the simulation technology: a binary and an attenuated phase-shifting mask. The binary masks, which were fabricated by Toppan Chunghwa Electronics (TCE; Padeh City, Taiwan), were 6 x 6 x 0.25 in. in size and made of standard chrome on glass.

To simulate the real defects found in the production environment, TCE supplied scraped masks that contained natural defects. In some instances, defects were either enhanced or added to the masks using either an 8000 advanced photomask repair system from Micrion (Peabody, MA) or a C-SL453X repair tool from NEC (Tokyo). The objective was to create defects that represented poor repairs.

The attenuated or halftone mask, which was fabricated by Photronics-PSMC (Hsinchu, Taiwan), utilized a MoSiON absorber with 6% transmittance and 180° phase. The programmed-defect test site, the Defect Sensitivity Monitor designed by ASML MaskTools (Santa Clara, CA), contained a series of seven programmed defects within a line/space pattern. Both 0.55-µm and 0.35-µm pitches with the nominal 0.15-µm (1x) line features were designed. The sizes of added defects were 0, 30, 40, 50, 60, 70, and 80 nm (1x). The masks were inspected with the 305UV reticle inspection tool from KLA-Tencor (San Jose). The tool's die-to-die (D2D) mode was used to generate defect-highlight images, and its Starlight mode was used to generate mask images utilizing the snapshot function.

Wafer exposures were obtained on ASML's PAS5500/550 scanner with 4x reduction using UMC's 0.18-µm generation deep-ultraviolet process. For the line/space structures, the numerical aperture was 0.60 and the coherence factor was 0.75, with the exposure energy targeting a CD of 180 nm on the reference line for the binary mask and 150 nm for the attentuated mask. An 8820 CD-SEM from Hitachi Scientific Instruments (Pleasanton, CA) was used to generate the SEM images.

Wafer-image simulations were performed using Virtual Stepper software version 2.1. For the line/space mask image using the D2D inspection mode, the mask pixel size was set to 186 nm with a grid size of 46.5 nm. The final simulation pixel size was 11.625 nm. For the line/space mask image using the Starlight inspection mode, the mask pixel size was set to 37.5 nm with a grid size of 9.375 nm. The final simulation pixel size was 9.375 nm. In each case, CD-SEM measurements from actual printed wafers were compared with what the Virtual Stepper simulation predicted for the same features at the best focus.

Results and Discussion

The technology assessment examined a wide variety of defect types across two different mask types to determine the overall accuracy of the simulation. Tip-to-tip and line intrusions, tip-to-tip and line protrusions, pin-dots, pinholes, and one example of a particle-type defect were assessed. These data are summarized in Table II. Compared with the wafer results, the reference images had an overall simulation accuracy of >99%. Compared with the defective areas on the wafer, the defective areas of the reference images had an average accuracy of >97%.

Figure Number Mask Type Defect Type Simulation Reference Wafer Reference D Simulation Definition Wafer Definition D 1 Binary Intrusion 380 380 0 Broken line — — 2 Binary Intrusion 370 370 0 340 346 6 3 Binary Protrusion 295 296 1 278 273 5 4 Binary Pin-dot 250 248 2 238 234 4 5 Binary Pinhole 370 368 2 319 346 27 7 Attenuated Protrusion 156 156 0 191 189 2 8 Attenuated Protrusion 137 137 0 190 193 3

Table II: Defect and mask types that were investigated to assess the simulation technology.

In all the figures presented here, the first image (a) is an optical image from the inspection tool, the second image (b) is a simulated image, and the third image (c) is a SEM wafer image. The effect of these defects was quantified by generating Bossung plots (d) showing feature size versus defocus. Other quantification methods include intensity plots, feature size versus exposure level analysis, and process latitude trade-off curves.

Figures 1 and 2 show chrome-intrusion–type defects. Figure 1 shows a rather severe chrome intrusion on a 380-nm line. The simulation showed this defect to be significant, as confirmed by the accompanying wafer image. The Bossung plot in Figure 1d shows no value for the defect area, since this defect caused a line break that results in no measurable linewidth at that point. The defect in Figure 2 also is a chrome-intrusion defect, but it is less severe than that shown in Figure 1. The Bossung plot in Figure 2d indicates that while this defect caused the depth of focus to be reduced by 50%, there was still approximately 500 nm of useful depth of focus within the ±10% CD window. Such a borderline result would be acceptable if necessary. These data validate the ability of the simulation software to reliably quantify the same type of defect in very different environments.

Figure 1: Optical (a), simulated (b), and SEM (c) wafer images of a severe chrome intrusion on a 380-nm line. The simulation and SEM wafer image show the defect to be significant. The Bossung plot (d) shows no value for the defect area, since this defect caused a line break that resulted in no measurable linewidth at that point.

Figure 2: Optical (a), simulated (b), and SEM (c) wafer images of a less-severe chrome-intrusion defect than that in Figure 1. The Bossung plot (d) indicates that while this defect caused the depth of focus to be reduced by 50%, there was still approximately 500 nm of useful depth of focus through the full focus window.

Figure 3 shows a tip-to-tip chrome-protrusion defect on a binary mask. While the agreement between the simulated image and SEM wafer image is very good, the impact of the defect on the printed image is usually determined in a very qualitative fashion. Production workers with years of experience ultimately make the call as to how and to what degree a defect will affect the electrical performance of the device of which this pattern is a part. This determination is done indirectly, by judging the effect the defect will have on the printed image. However, being able to quantify this assessment process is mandatory if an automated method of assessment is going to be implemented. The Bossung plot in Figure 3d quantifies the defect's impact on the printed image. By adjusting the exposure level, it is likely that this feature could be brought back to nominal, if required. Otherwise, it is clearly within the ±10% CD specification.

Figure 3: Optical (a), simulated (b), and SEM (c) wafer images of a tip-to-tip chrome-protrusion defect on a binary mask. The Bossung plot (d) quantifies the defect's impact on the printed image. The feature is within the ±10% CD specification.

Figure 4 shows a chrome pin-dot, a nuisance defect that would have little or no effect on the printed image. The Bossung plot in Figure 6d shows that the ±10% CD specification was easily met through the full range of defocus. In many instances, it would be unnecessary to repair this type of defect or a defect of similar severity. The repair process would endanger overall plate quality and increase turnaround time.

Figure 4: Optical (a), simulated (b), and SEM (c) wafer images of a chrome pin-dot, a nuisance defect that would have little or no effect on the printed image. The Bossung plot (d) shows that the ±10% CD specification was easily met through the full range of defocus.

Figure 5 presents a pinhole. Such a defect can either be a nuisance-type defect if it occurs in a large chrome area or, as in this case, can have a significant impact on the feature. The Bossung plot in Figure 5d clearly indicates that the line-width in the area of the defect is well outside the acceptable range of the specification.

Figure 5: Optical (a), simulated (b), and SEM (c) wafer images of a pinhole. The Bossung plot (d) indicates that the linewidth in the area of the defect is well outside the acceptable range of the specification.

Figure 6 depicts a chrome-residue defect and is quite different from the other defect types. While no specific analysis was performed on this defect, it illustrates the performance of the simulation tool in an unstructured (nonprogrammed defect) environment. The size of the defect on the mask was approximately 20 sq µm (5 x 4 µm).

Figure 6: Optical (a), simulated (b), and SEM (c) wafer images of a chrome-residue defect, illustrating the performance of the simulation tool in an unstructured (nonprogrammed defect) environment.

Figures 7a, b, and c illustrate the programmed protrusion defect with defect ID 54 in Figure 7d. That figure summarizes the results of defect evaluation testing on a line/space pattern with a pitch of 0.55 µm. These data show very good agreement between the simulation software's predictions and actual wafer CD measurements.

Figure 7: Optical (a), simulated (b), and SEM (c) wafer images of the programmed protrusion defect with defect ID 54 (d). These data show very good agreement between the simulation software's predictions and actual wafer CD measurements.

Figures 8a, b, and c illustrate the programmed protrusion defect with defect ID 49 in Figure 8d. That figure summarizes the results of defect evaluation testing on a line/space pattern with a pitch of 0.35 µm. These data points again show very good agreement between the simulation software's predictions and the actual wafer CD data.

Figure 8: Optical (a), simulated (b), and SEM (c) wafer images of the programmed protrusion defect with defect ID 49 (d). These data show very good agreement between the simulation software's predictions and the actual wafer CD measurements.

Conclusion

Based on evaluations by UMC, it is clear that the simulation tool has the ability to repeatably and accurately forecast the wafer image of a variety of defects. The technology was shown to accurately simulate a range of defect types that appear on both binary and attenuated phase-shift masks. It also was shown to be independent of inspection tool wavelength. The results of this study are consistent with previously published data (presented in Table I) and demonstrate that a wide variety of defects discovered in a production environment can be quantified with ease in that environment.

Acknowledgments

The authors would like to acknowledge the contributions of Steve Tuan from TCE and Vincent Hsu and David Wu from KLA-Tencor in Taiwan, who provided the test masks and helped capture mask images. They also wish to thank Numerical's Kevin Chan and Mark Altamarino, who performed simulations and data collection, and Fang-Cheng Chang, who provided technical and management support.

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