INDUSTRY NEWS

X architecture marks the spot for good yields, supporters say

GOODBYE, MANHATTAN: A screen capture of an X architecture design shows diagonal routing on a chip's top two metal layers.

A reputed breakthrough in interconnect technology promises high yields because the technology reduces both die size and the number of vias compared with the standard interconnect process, according to backers of the major development effort. Called the X Initiative, the new five-year program is billed as the first attempt to develop a mass-production method that maximizes the potential of diagonal interconnects.

Supporters say the diagonal technique reduces chip wiring by greater than 20%, increases chip performance by more than 10%, and produces at least 30% more chips per wafer for system-on-chip (SOC) ICs and other devices with multiple metal layers. X architecture keeps the standard right-angle "Manhattan" architecture on metal layers one through three before rotating the interconnects by a 45° angle in layers four, five, and higher. As a result, the wires can be sent in eight different directions, reducing the average length of wiring in the chip by 20%.

The yield improvements are tied to a combination of factors, asserts Aki Fujimura, president and COO of Simplex Solutions. The Sunnyvale, CA–based software and design services provider has teamed with Toshiba to lead the initiative. "What we are experiencing is that we can reduce the die size by 15% or more, and we can reduce the number of vias on the design by over 30%. The combination of the two effects—the size reduction and the via reduction—produces an average of 30% more working chips per wafer.

"That yield really comes from two different things," Fujimura adds. "One is process yield...and the other is timing yield." He notes that finished wafer lots frequently show chips testing at a variety of different speeds—some at 250 MHz, others at 230 MHz, and still others at 350 MHz. "There's a wide variation because the process variation is actually becoming more and more of a problem as we go deeper and deeper into the submicron realm."

Vias have very high statistical variations in actual resistance per via, he emphasizes, "because you have to line them up together. This resistance variation timing causes big yield problems. Reducing the vias by more than 30% contributes to better yield."

Dave Hanson agrees. He is the business unit manager, benchmark services, for PDF Solutions, a provider of yield-management services and a member of the initiative. Via failure rates are "a dominant driver" in SOC yields, he emphasizes. "If you have 30% fewer vias, your via-limited yield component is going to be much less, and your overall yield is going to be much higher."

A process line with Manhattan-style yields will create more usable die with diagonal routing, Hanson adds. The percentage improvements in chip performance and the wiring reductions are parameters connected directly to yield, he notes. "If you can get a 30% reduction in die area, that's also going to mean a huge impact in terms of the gross die per wafer that are going to be created. So even at the same yield rate, you're going to get more product per wafer."

In its work PDF has noted a new problem occurring with chips at the 0.25-µm node and below, what Hanson calls "layout-dependent yield loss. We focus mainly on that area, as opposed to concentrating on random defects." A number of techniques, including OPC and phase-shifting masks, can be used to correct such "pattern-dependent" yield loss.

The use of diagonal wiring does pose some questions without answers at this time, Hanson says. "There's a lot that's not clear" about which problems are "layout dependent," for instance, "or even what the electrical effects are...on features that are primarily 45° angles. A lot of the chips fabricated today don't really have that."

Expanding on Fujimura's comments, Hanson says problems related to resistance and capacitance "make extraction and design-rule checking more complicated than they were in the past. For mixed-signal system-on-chip products, your ability to close timing and finish the chip off is driven by the analog yield-loss component. The analog blocks in these mixed-signal SOCs...tend to limit the ability to bring the yield of the circuits up quickly. That yield is affected by the resistance and capacitance of the interconnect system, and because these things are running at diagonals, we don't know how accurate the resistance and capacitance are going to be."

Hanson sees confidence—perhaps warranted, perhaps not—among equipment manufacturers. "The tool providers think they have answers. It takes some volume [of production] and some experience. It's hard to predict how much time is going to be required, but we anticipate a lot of activity next year."

'If you have 30% fewer vias . . . your overall yield is going to be much higher.' — Dave Hanson, PDF Solutions

DuPont Photomasks (DPI) will be among the busy companies. A member of the initiative, the mask supplier faces some challenges uniquely related to the technology, notes Ken Rygler, executive vice president of worldwide marketing and strategic planning. Mask-writing tools, particularly vector scan tools, may take longer to operate, for instance. "Because of the way they write and the nature of the X architecture, the writing times will probably be longer than they would be with raster scanning machines."

Still, Rygler points out, "that in and of itself is not a showstopper, because most of the tools we have are raster scanners." For initial introduction of the X architecture at the 0.13-µm design rule node "we might have to use our vector-scan write tools. When you get to the three, four, and five metal layers then the specs tend to loosen somewhat, and we would use a raster scanning tool. In the long run, it won't be an issue."

Rygler also anticipates few problems in mask inspection. He says KLA-Tencor inspection systems, especially the most recent family of tools, "are really well suited for X architecture." DPI does have "a lot of the older-technology KLA-Tencor tools" that can be used in early developmental efforts.

The executive does see some cost issues on the horizon. "The longer one has to wait while utilizing a pattern generator, the more costly a mask is going to be. So, yes, you could have cost implications. We'll just make sure customers are aware of this."

Simplex and Toshiba spent more than two years collaborating on the development of a feasible X architecture concept. They have designed a RISC processor core as the inaugural design to use the diagonal wiring method. Toshiba says it plans to use the architecture in new designs beginning in 2002.

The concept has been around for a number of years, drawing more interest as chip geometries continue to shrink. Its use has been limited to custom-designed semiconductors, however. Simplex's invention of so-called liquid routing technology with no grids and octilinear wiring makes the concept practical for the first time, the company claims.

"To be precise, for several years people have had the concept of the gridless router that makes bends, if you will," explains Hanson. "That's been a useful technology, to a degree. Before that, there was basically a square, and you had to optimize placement of standard cells. Now they've created an octagon for packing the standard cells together and then doing the routing with short-link bends and things on diagonal angles as well as long runs on 45° angles."

Diagonal architecture creates a huge amount of data, Hanson notes. Despite the hurdles, toolmakers think they can overcome any problems, he believes. "I think the standard answer you'll find is that they can do all of this. The questions will be about speed and cost."

KLA-Tencor, one of the equipment companies involved in the initiative, praises Simplex for heading off potential inspection problems posed by the nature of diagonal routing. The acute angles that come to a sharp point "like the top of the letter 'A' tend to give inspection systems a little bit of a hard time," notes Lance Glasser, vice president and general manager of the RAPID division of KLA-Tencor. "There is a large difference between what the database says is supposed to be on the mask and what is actually written on the mask. That divergence is identified as a defect. In fact, it is a defect, but no one wants to see it. Simplex has responded to that issue. That's very good news."

There is no shortage of interest in the initiative. The membership encompasses the entire semiconductor industry food chain and includes IP companies, EDA firms, design services, chipmakers, and tool providers. The 14-member list also features Numerical Technologies, Etec Systems, Virtual Silicon, and Tensilica. One of the most recent recruits, STMicroelectronics, provided further proof to Fujimura that the semiconductor industry believes as he does.

"We started to talk with Toshiba about it three and a half years ago," Fujimura notes. "About two years ago, both companies became convinced that all of the initial barriers could be overcome. The reason they haven't been overcome before is, one, we hadn't thought persistently enough about them and, two, the benefits...were not thought to be that significant before."

He thinks the innovations in design such as the 20% wire reduction and 30% via reduction "are so compelling that people are now saying, 'Well, if it's that good I'm willing to go over some hurdles to solve some of the problems.' "

The X Initiative Web site is http://www.xinitiative.org.

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