MICRO: Implementing SiGe technology to produce heterojunction bipolar transistors

The performance and integration capability of SiGe devices has enabled the production of a wide range of new products for wireless and wired communications, high-speed-test, and disk-drive applications. SiGe products include chip sets for wireless cellular handsets and base stations, as well as wireless local area network and high-speed/high-capacity wired network applications.^3–6

SiGe HBTs outperform previous devices because the addition of germanium to the base of a device results in a lower-energy bandgap. Germanium is added in situ during the epitaxial growth of the HBT base. Depending on the technology generation, SiGe HBT devices have cutoff frequency (f_t) performance values ranging from 47 to 120 GHz and maximum oscillation frequency (f_max) values from 65 to 100 GHz.^7–10 In addition to high-performance SiGe HBT devices, an NPN device featuring a high-breakdown-voltage collector to emitter exists for applications such as power amps.⁸

The integration of SiGe HBT with existing CMOS technologies has enabled the rapid introduction of new SiGe BiCMOS technologies. Volume production of two SiGe technology generations, 0.5 and 0.24 µm, is currently being performed at IBM's semiconductor fab in Essex Junction, VT. A third technology generation, 0.18 µm, is moving from development to production.

This article reviews some of the challenges facing SiGe manufacturing. Most of the data have been gathered from tests conducted on IBM's 0.5-, 0.24-, and 0.18-µm SiGe BiCMOS technologies.^7–9,11,12 The foremost challenge is the growth of the SiGe epitaxial layer and its integration with standard CMOS processes. Another challenge relates to device yield issues (such as long-term yield trends) affecting both NPN and CMOS devices. A third challenge is the production of passive devices, which involves in-line process improvements that can translate into improved device centering and control. The article will conclude with a discussion of challenges and opportunities facing future SiGe technology generations.

Depositing SiGe Using Low-Temperature Epitaxy

The development of the ultrahigh-vacuum/chemical vapor deposition (UHV/CVD) method for depositing epitaxial silicon was the enabling force behind SiGe technology. Passivating the wafer surface with hydrogen and performing UHV/CVD at temperatures <850°C results in an epitaxial film that is practically defect-free (<10³ defects/cm²).¹³ This low-temperature epitaxy (LTE) process enables abrupt, fully activated in situ boron doping¹⁴ and the controlled incorporation of germanium into the silicon lattice. Applied to bipolar and BiCMOS technologies, LTE replaces the implanted base (which is common in homojunction NPNs produced through conventional epitaxy) with an in situ–grown base and graded germanium HBT.¹⁵

The LTE process grows epitaxial silicon over the exposed HBT silicon regions and polysilicon over regions that are protected by polysilicon or silicon dioxide. An SEM micrograph of an HBT formed through LTE is shown in Figure 1.
	Figure 1: SEM image of a SiGe HBT after complete processing.

The SiGe epitaxial base region is contacted by the polysilicon that is formed over the shallow trench isolation (STI) during LTE deposition.

As SiGe technology has migrated into mainstream production, the capabilities of the UHV/CVD process have steadily improved to meet growing demand. While the fundamental technique has remained unchanged since its development in the mid-1980s, the steady evolution of diverse manufacturing elements, from hydrogen passivation to tooling design, has produced a more productive process and improved uniformity and film quality.

As documented elsewhere, the passivation of the wafer surface with hydrogen is critical to the success of the LTE process.¹³ While a wafer can be treated with dilute hydrofluoric acid followed by air drying to produce a hydrogen-passivated wafer surface, this procedure is susceptible to human error and depends on an integration scheme using a protective polysilicon layer to provide a largely hydrophobic surface.² Concerted process development efforts have led to a manufacturable solution using a commercially available, SPC-controlled tool to perform the passivation process. The result is a repeatable process that does not have a discernible impact on yield and does not depend highly on integration to produce a safe, dry, passivated surface.

In the past, low LTE productivity was a considerable manufacturing concern. Batch sizes were limited by the lack of wafer-to-wafer uniformity and the linear depletion of the dopant species. That depletion was a direct consequence of molecular flow, a tube design that minimized the pumped volume of gas, and the large wafer loads employed in the manufacturing process. Of all the solutions considered, a simple modification of the gas-delivery system improved uniformity and enabled engineers to increase batch sizes. Furthermore, the loader assembly was modified to sustain larger batch loads, leading to a 100% increase in batch size as well as wafer uniformity improvements.

While advancing productivity, the modification of the UHV/CVD gas-delivery system also proved beneficial to parametric control. This change effectively eliminated the linear depletion associated with the original design. As shown in Figure 2, the implementation of the new design improved pinch-base sheet resistance. Since base profile plays a significant role in the function of SiGe NPNs, the benefits of improved uniformity could be measured across a broad range of NPN parametrics. Figure 3 presents wafer-to-wafer uniformity improvements for the pinch-base sheet resistance, emitter-base breakdown voltage (BVebo), transistor current gain (Beta), and base-emitter forward voltage (Vbe). Data gathered over a 90-day period on a system with the improved design demonstrated that this design led to a 24–42% improvement in wafer-to-wafer uniformity while batch size increased by 50%.

Figure 2: Modifying the gas-delivery system had a beneficial effect on the pinch-base sheet resistance of 0.5-µm SiGe BiCMOS devices.

Figure 3: Parametric uniformity improvements for the pinch-base sheet resistance, emitter-base breakdown voltage (BVebo), transistor current gain (Beta), and base-emitter forward voltage (Vbe) of 0.5-µm SiGe BiCMOS devices resulting from modifying the UHV/CVD gas-delivery system.

SiGe BiCMOS Process Integration

The key issue for developing a SiGe BiCMOS process involves choosing an integration method that minimizes the interaction of HBT and CMOS processing steps. Generally, it is preferable to add the SiGe HBT to an existing CMOS technology, maintaining the parent CMOS technology's field-effect transistor (FET) characteristics so that existing cell libraries and ASIC design methodologies can be used. In addition, an HBT process that has features in common with a parent CMOS process can use CMOS process learning and manufacturing line controls. However, it is important to minimize the impact of CMOS processing steps on bipolar device performance.

The 0.5-µm-generation SiGe BiCMOS technologies use a base-equal-gate integration method.^{7, 11} With that approach, the growth and patterning of the NPN SiGe epitaxial base also forms the FET polysilicon gates. Sharing layers and thermal cycles works well because the number of overall steps is minimized.

However, implementing that approach became more difficult when thermal cycle changes appeared in subsequent CMOS generations. To maintain a narrow-base, high- performance HBT, it is necessary to limit and control the heat that the base is exposed to. But CMOS technologies require high temperatures for arsenic source/drain dopant activation and lateral "bird's beak" minimization during gate sidewall oxidation. To overcome this thermal cycle incompatibility, a base-after-gate integration scheme was developed for the 0.24-µm SiGe BiCMOS technology.⁸ Figure 4 compares a base-equal-gate and base-after-gate process flow. In the base-after-gate approach, the HBT is built after the FET anneals, minimizing the thermal cycles that the SiGe base is exposed to. Since HBT processing, including epitaxial processing, occurs at low temperatures, the thermal effect on the FET is minimal. Moreover, the base-after-gate approach is modular. This modularity makes the HBT more compatible with other generations of CMOS technologies and can simplify the creation of derivative technologies.

Figure 4: Comparison of base-equal-gate and base-after-gate integration methods. The base-equal-gate method uses process sharing while the base-after-gate method is modular, with the HBT process being run after the FET thermal cycles.

The base-after-gate approach poses unique challenges. All films deposited during HBT process steps must be completely removed from over the FET gates without forming extraneous spacers or causing defects in the already-created gate structure. Advances in reactive ion etch technology have enabled the removal of these films, as demonstrated in the yield-trend data from large-area CMOS defect monitors presented in Figure 5 and the yield data from a 154k CMOS SRAM presented in Figure 6. These yields are within the parent CMOS technology target range.

Figure 5: Yield-trend data from CMOS defect monitors built in 0.24-µm SiGe BiCMOS technology. The nominal yield is within 3–4% of parent CMOS devices.

SRAM yield data also indicate the successful resolution of another integration challenge, which results from the topography of the HBT base and emitter stack. Covering this stack at the contact level requires a thicker dielectric than is usually used in the parent CMOS process. The higher contact aspect ratio associated with this increased dielectric thickness made it necessary to enhance the CMOS contact etch and liner deposition processes. These enhancements were necessary to achieve the desired SRAM yield.

Figure 6: Yield-trend data for 154k CMOS SRAM devices (12-µm² cell size) manufactured using 0.24-µm SiGe BiCMOS technology.

	These integration solutions have led to the production of highly integrated products, such as the 0.24-µm SiGe BiCMOS partial-response-maximum-likelihood read channel chip illustrated in Figure 7.
Figure 7: Image of a 0.24-µm SiGe BiCMOS partial-response-maximum-likelihood read channel chip.

SiGe HBT Device Yield

NPN device yield has always been an issue with silicon bipolar and BiCMOS technologies. Yield is usually limited by dislocations in the silicon crystal, which cause emitter-to-base, collector-to-base, or collector-to-emitter shorts. These dislocations are even more likely with SiGe HBTs because of the potential for defect formation during epitaxial growth and as a result of strain in the Ge layer. But the LTE process produces a relatively defect-free epitaxial layer that does not contribute to yield loss. Minimizing thermal cycles following epitaxial growth helps reduce the possibility of defects that form as a result of the strained layer. The primary source of defect generation in LTE-produced SiGe devices is related to stress from the edges of STI regions.

The effect of STI on HBT yield was studied extensively in the 0.5-µm technology generation. Transmission electron microscopy analyses of low-yielding samples showed dislocation defects arising from the top or bottom corners of STI regions adjacent to the HBT. These analyses suggested that the HBT was not in stress equilibrium with the surrounding STI regions. It was found that the shape of the STI regions adjacent to the HBT affected how the transition region between epitaxial silicon and polysilicon in the SiGe epitaxial film formed. The shape of this transition region greatly influences stress in the HBT. Optimization of the STI shape reduced that stress, leading to fewer dislocations and significantly higher HBT yield. Figure 8a shows an SEM cross section of an SiGe NPN where the STI shape has not been optimized. A significant divot was formed at the top corner of the STI feature adjacent to the NPN, resulting in poor NPN yield. Figure 8b shows a cross section of a device with an optimized STI shape. This device has a more planar STI surface adjacent to the NPN and results in correspondingly higher NPN yield.

Figure 8: SEM images of cross sections of a 0.5-µm SiGe BiCMOS NPN device: (a) with a nonoptimized STI shape, and (b) with an optimized STI shape.

Figure 9 shows a 20-month NPN yield-trend chart of an array of 4000 HBTs. If any one of the 4000 NPN transistors in the array is defective, the whole array is considered bad. The yield of the 4000 NPN array is measured at 18 sites across the wafer and is calculated by dividing the number of good sites by the total number of sites. Before STI process optimization, yield was quite low, averaging in the 60–70% range. After optimizing the STI shape adjacent to the HBT, yield improved immediately by 20%. Also, by optimizing STI in-line process controls to reduce variability, yield was further improved, so that the process regularly runs above 90% now. Sustaining high-yield performance requires ongoing monitoring of key in-line process metrics. In other words, differences between tools running the same process must be minimized, process shifts must be addressed and corrected quickly, and process contamination levels must be kept low and in control.

Figure 9: Monthly yield trend of an array of 4000 NPN transistors in 0.5-µm SiGe BiCMOS technology. Yield increases resulted from STI process recentering and improvements in STI controls.

The high-yield capability of the LTE SiGe process has translated into high-volume production of devices containing more than 30,000 HBTs and more than one million FETs. The acquired process learning has been incorporated into the 0.24-µm process, which regularly produces 4000-HBT-array yields above 90%.

Additional Technology Components

In order to improve analog circuit performance, it is essential to integrate high-quality passive devices into standard HBT and logic CMOS circuitry. Such passive devices include analog FETs, precision resistors, metal-oxide-silicon (MOS) and metal-insulator-metal (MIM) capacitors, and high-Q inductors. Other process modules have been developed to enable the manufacture of these devices.

CMOS logic devices are optimized for low-voltage logic applications. Analog designs require FETs that can operate at higher voltages. These components are manufactured by including a dual-gate-oxide option that permits logic and analog devices to coexist on the same die.⁸

Precision resistors with a wide range of sheet resistance values can be constructed by using existing CMOS/bipolar implants or a dedicated implant in silicon or polysilicon. Polysilicon resistors are preferred because of their favorable thermal coefficient of resistance and low capacitance. Optimal resistor tolerance can be achieved by carefully controlling several key manufacturing steps that affect the electrical properties of the device, including polysilicon morphology, implant dose, thermal activation and deactivation, and silicide formation.

MOS capacitors are formed with gate oxide and gate polysilicon above a highly doped silicon region. The high doping of the silicon bottom plate helps minimize the capacitors' voltage dependence.^{9, 16} High-quality, thermally grown gate oxides enable the production of reliable capacitors with large capacitance per unit area. The development of MIM capacitors has provided designers with an additional capacitor option that has low series resistance, low parasitic capacitance, and very low voltage dependence.¹⁷

Inductors are made with spirals of one or more metal layers. The Q of the inductor is limited mostly by the resistance of the metal spiral and the degree to which the metal spiral couples with the silicon substrate. The metal resistance and substrate coupling worsen with each technology generation because the metal layers and intermetal dielectric become thinner. One approach to overcoming this problem has been to add an optional thick metal module to the process. Such an add-on module, which includes a 3-µm-thick dielectric and 4-µm-thick metal, is added above the standard wiring levels. This approach has led to the production of inductors having Q values between 15 and 20.¹⁸

Experience has shown that products may exhibit circuit limited yield (CLY) issues as a result of parametric variation in passive devices. Typically, process window experiments are run for new designs to identify CLY issues. In some instances, device specifications may require adjustments to reflect the actual performance of the device.

Device centering and tolerance have been improved in passive devices built onto SiGe technologies. For example, Figure 10 shows the process capability index (C_pk) for a 210- W/sq polysilicon resistor. Centering was accomplished by adjusting the dose of the boron ion implant based on the results of process window experiments. Further tolerance improvements were accomplished by optimizing key thermal activation and deactivation processes to improve lot-to-lot, wafer-to-wafer, and within-wafer variance. Moreover, statistical process control methods are utilized to maintain tight process and tool control. Process or tool instabilities, including differences between tools, are quickly highlighted and corrective actions are taken to maintain device stability.

Figure 10: Monthly C_pk performance for a 210-W/sq polysilicon resistor to a ±20% tolerance. Data are from 0.24-µm SiGe BiCMOS technology.

Figure 11 shows another example of C_pk improvement for a 1.5-fF/µm² decoupling capacitor. Following initial instability, line centering and process controls were implemented to improve the device.

Figure 11: Monthly C_pk performance for a 1.5-Ff/µm² decoupling capcitor to a +10% tolerance. Data are from 0.5-µm SiGe BiCMOS technology.

Conclusion

IBM has initiated volume production of its third generation of SiGe technology and is in the process of moving 0.18-µm SiGe technology from development to a production facility.¹⁹ Past production experience will aid in the development of next-generation SiGe technologies.

The challenge facing next-generation technologies is to enhance FETs, HBTs, and additional components. Also, the broad range of applications, which have their own requirements, will demand multiple versions of each technology generation. Modular integration approaches, such as the base-after-gate approach, can simplify the development of such derivative technologies. Continued emphasis on process and tool control will be required to achieve the necessary parametric uniformity and low defect densities demanded by future technologies.

FET enhancements can be adopted from CMOS technologies that are already in production. Applying these enhancements to the BiCMOS process without modifying the CMOS or HBT will be challenging. The base-after-gate integration method can simplify that task because it is modular and isolates the HBT from CMOS thermal cycles.

It is likely that the HBT will undergo both vertical and horizontal scaling. Horizontal scaling can be achieved by adopting the photolithography process and tool improvements that have been implemented to produce CMOS devices. Shrinking the HBT requires shrinking the wires feeding into the device. Electromigration caused by shrinking these wires can be alleviated by using copper interconnects. Vertical scaling can be achieved by modifying the LTE profile and minimizing the diffusion of the base and collector dopants. A modular integration approach, such as base-after-gate, can help reduce diffusion by minimizing the thermal cycles that the HBT undergoes. Recent advances in rapid thermal processing may also prove beneficial in reducing the overall thermal budget.

Some possible enhancements to passive components include the use of low-k dielectrics to reduce the parasitic capacitance of inductors, capacitors, and resistors and high-k dielectrics to increase capacitors' capacitance per unit area. Furthermore, the continuing drive to decrease the thickness of metal and dielectric layers will create the need for an increasingly thick metal add-on module for building inductors.

References

1. DL Harame et al., "Si/SiGe Epitaxial-Base Transistors—Part I: Materials, Physics, and Circuits," IEEE Transactions on Electron Devices 42, no. 3 (1995): 455–468.

2. DL Harame et al., "Si/SiGe Epitaxial-Base Transistors—Part II: Process Integration and Analog Applications," IEEE Transactions on Electron Devices 42, no. 3 (1995): 469–482.

3. R Lodge, "Advantages of SiGe for GSM RF Front Ends," Electronic Engineering(UK) 71, no. 865 (1999): 18–19.

4. R Gotsfried et al., "RFIC's for Mobile Communication Systems Using SiGe Bipolar Technology," IEEE Transactions on Microwave Theory 46, no. 5, pt. 2 (1998): 661–668.

5. "AMCC Introduces the Industry's First 10 Gbps Silicon Germanium OC-192 SONET/SDH Limiting Amplifier," in AMCC Home Page [on-line] (San Diego: AMCC, 1999 [cited October 11, 1999]); available from Internet: http://www.amcc.com/Compinfo/PressReleases/S3096pr.html.

6. "AMCC Demonstrates Industry's First 40 Gbps Eye Diagram from a SiGe-Based Interface Device, Exhibited at New Customer Demonstration Lab," in AMCC Home Page[on-line] (San Diego: AMCC, 2001 [cited May 2, 2001]); available from Internet: http://www.amcc.com/Compinfo/PressReleases/40gig_demolab.html.

7. DC Ahlgren et al., "A Si-Ge Technology for the Wireless Marketplace," in Proceedings of the European Solid State Device Research Conference '96 (Paris: Aditions Frontieres, 1996), 453–456.

8. SA St.Onge et al., "A 0.24-µm SiGe BiCMOS Mixed-Signal RF Production Technology Featuring a 47 GHz f_t HBT and 0.18-µm Leff CMOS," in Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (Piscataway, NJ: IEEE, 1999), 117–120.

9. G Freeman et al., "A 0.18-µm 90 GHz f_t SiGe HBT BiCMOS, ASIC-Compatible, Copper Interconnect Technology for RF and Microwave Applications," in Proceedings of the International Electron Devices Meeting (Piscataway, NJ: IEEE, 1999), 569–572.

10. A Joseph et al., "A 0.18-µm BiCMOS Technology Featuring 120/100 GHz (f_t/f_max) HBT and ASIC Compatible CMOS Using Copper Interconnect" (paper to be presented at the Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, October 2–4, 2001).

11. D Nguyen-Ngoc et al., "A 200 mm SiGe HBT BiCMOS Technology for Mixed-Signal Applications," in Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting(Piscataway, NJ: IEEE, 1995), 89–92.

12. DC Ahlgren et al., "Manufacturability Demonstration of an Integrated SiGe HBT Technology for Analog and Wireless Marketplace," in Proceedings of the International Electron Devices Meeting (Piscataway, NJ: IEEE, 1996), 859–862.

13. BS Meyerson, "Low-Temperature Silicon Epitaxy by Ultrahigh Vacuum/Chemical Vapor Deposition," Applied Physics Letters 48, no. 12 (1986): 797–799.

14. BS Meyerson et al., "Non-Equilibrium Boron Doping Effects in Low-Temperature Silicon Films," Applied Physics Letters 50, no. 2 (1987): 113–115.

15. DL Harame et al., "Epitaxial-Base Transistors with Ultrahigh Vacuum Chemical Vapor Deposition (UHV/CVD) Epitaxy: Enhanced Profile Control for Greater Flexibility in Device Design," IEEE Electron Device Letters10, no. 4 (1989): 156–158.

16. SA St.Onge et al., "Design of Precision Capacitors for Analog Applications," in Proceedings of the Electronic Components and Technology Conference(Piscataway, NJ: IEEE, 1992), 583–590.

17. K Stein et al., "High Reliability Metal Insulator Metal Capacitors for Silicon Germanium Analog Applications," in Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (Piscataway, NJ: IEEE, 1997), 191–194.

18. R Groves et al., "High Q Inductors in a SiGe BiCMOS Process Utilizing a Thick Metal Process Add-On Module," in Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (Piscataway, NJ: IEEE, 1999), 149–152.

19. S Subbanna et al., "Integration and Design Issues in Combining Very-High-Speed Silicon-Germanium Bipolar Transistors and ULSI CMOS for System-on-a-Chip Applications," in Proceedings of the International Electron Devices Meeting (Piscataway, NJ: IEEE, 1999), 845–848.

Mark D. Dupuis is involved in process integration for silicon germanium BiCMOS technologies at IBM's facility in Essex Junction, VT. He joined the company in 1979 as a process engineer working with low-pressure chemical vapor deposition processes for silicon and dielectric films. In 1979 he received a BS in engineering physics from the University of Maine in Orono, and in 1985 he received an MS in materials science from Syracuse University in Syracuse, NY. (Dupuis can be reached at 802/769-8332 or dupuis@us.ibm.com.)

Stephen St.Onge is manager of mixed-signal technology development at IBM's semiconductor facility in Essex Junction, VT, and has engaged in the development of bipolar, BiCMOS, and silicon germanium BiCMOS technologies since joining the company in 1982. In 1982 he received an AS in electrical engineering technology from Vermont Technical College in Randolph Center and in 1992 he received a BS in electrical engineering from the University of Vermont in Burlington. (St.Onge can be reached at 802/769-7457 or sstonge@us.ibm.com.)

Ryan Wuthrich is a process engineer for ultrahigh-vacuum/ chemical vapor deposition of LTE SiGe at IBM's facility in Essex Junction, VT. He joined IBM in 1988. Wuthrich has been associated with the LTE process for four years and was involved in the transfer of the technology from the Advanced Semiconductor Technology Center in East Fishkill, NY, to IBM's Essex Junction facility. He received a BS in mechanical engineering from Purdue University in West Lafayette, IN, and an MS from Rensselaer Polytechnic Institute in Troy, NY. (Wuthrich can be reached at 802/288-3453 or wuthrr@us.ibm.com.)

Heidi L. Greer works in process integration for SiGe BiCMOS technologies at the IBM facility in Essex Junction, VT. Formerly she was a process engineer for polysilicon LPCVD films. She has a BS in chemical engineering from the University of Massachusetts (Amherst) and is pursuing an MS in microelectronics manufacturing engineering from Rensselaer Polytechnic Institute in Troy, NY. (Greer can be reached at 802/769-4109 or greerh@us.ibm.com.)

Steven S. Williams is involved in device parametric characterization for silicon germanium BiCMOS technologies at the IBM facility in Essex Junction, VT. He joined the company in 1985 as a process engineer working with PECVD dielectric films. In 1985 he received a BS in chemical engineering from Rensselaer Polytechnic Institute in Troy, NY, and in 1990 he received an MS in electrical engineering from Syracuse University in Syracuse, NY. (Williams can be reached at 802/288-3528 or sswillia@us.ibm.com.)

Thomas W. Weeks works in device and product characterization for silicon germanium BiCMOS technologies at the IBM facility in Essex Junction, VT. He joined IBM in 1980 and has worked as a process engineer in reactive ion etch, photo, ion implant, and process integration. He received a BS in electrical engineering from the University of Maine in Orono, an MS in electrical engineering from the University of Vermont in Burlington, and an MS in manufacturing systems engineering from Rensselaer Polytechnic Institute in Troy, NY. (Weeks can be reached at 802/769-9485 or tomweeks@us.ibm.com.)

William J. Miller is the project manager of electrical functional characterization for semiconductors produced in IBM's Essex Junction facility, which he joined in 1979. With extensive experience in semiconductor engineering, including in the fields of photolithography, reactive ion etch, and thin-film technologies, he is involved in the introduction, fabrication, and yield learning of advanced semiconductor products such as microprocessors, ASICs, analog devices, and RF semiconductors in aluminum, copper, silicon-on-insulator, and SiGe technologies. He received a BA in biology from Ithaca College in Ithaca, NY. (Miller can be reached at 802/769-8342 or willmill@us.ibm.com.)

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