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Testing self-primed spin-on low-k materials to optimize the cost of ownershipJoost J. Waeterloos, Dow Chemical/IMEC; and Michael E. Mills, Dow Chemical Significant process-cost savings could be achieved by including an adhesion promoter in spin-on dielectric formulations.
Historically, decreases in device geometries have fueled increases in the speed of logic devices and corresponding reductions in production costs, but as the industry approached the 180-nm technology node, the performance limitations of traditional aluminum and silicon dioxide (SiO2) interconnects made it more difficult for chipmakers to design their way to more speed. One industry response was to replace aluminum with copper, which is significantly less resistant and thus reduces resistance-capacitance time delays. The emergence of copper damascene metallization technology has already led to wafer-level cost reductions with demonstrated yield enhancements. Similarly, the current transition from SiO2 films to low-k interlayer dielectric (ILD) materials represents the industry's latest effort to sustain Moore's Law. Although low-k dielectrics were available in the late 1980s and early 1990s, it was unclear at that time whether these materials would be used first in subtractive technology, introduced at the same time as copper, or adopted later, after a copper-in-silicon-dioxide transition period. The 1995 edition of the National Technology Roadmap for Semiconductors (which became known as the International Technology Roadmap for Semiconductors, or ITRS, with the 1999 update) projected the use of low-k dielectrics with aluminum interconnects at 250 nm, but the introduction of these new materials was delayed in favor of SiO2 films applied using fluorinated silica glass chemical vapor deposition (FSG CVD) technology. The 1997 roadmap also called for the adoption of low-k materials in a hybrid scheme with aluminum-based integration technology, but at the 180-nm node. IBM's move to copper interconnects in that same year, however, set off a rush by other chipmakers to announce copper-technology production plans and pushed back low-k decisions even further, to the 130-nm generation. Now, after many false starts, several chipmakers have announced production capabilities for low-k 130-nm chip designs, and low-k materials have finally assumed their anticipated place on the ITRS schedule. Optimizing Deposition Processes As full-scale production with low-k ILDs begins in earnest, chipmakers will need to choose a manufacturing process that optimizes performance while minimizing COO. Figure 1 shows a comparison of COO models for the two most likely candidates: spin-on and CVD technologies. IBM made its choice in April 2000, opting for SiLK semiconductor dielectric resin from Dow Chemical (Midland, MI) for its copper dual-damascene processes. The ILD deposition technique being used has been optimized for both performance and COO by eliminating a buried etch-stop layer.1 Figure 2 shows a schematic of the ILD stack configuration, which reduces ILD-layer deposition costs by nearly 50% by eliminating one low-k spin-on dielectric (SOD) deposition step, as well as the etch-stop layer. The ability to integrate both the via and trench of the dual-damascene interconnect layer from a single layer of dielectric resin differentiates this technology from the others being considered for use at 130 nm and delivers a very low effective dielectric constant (keff), which dictates product performance.
This article focuses on another opportunity for improving the COO of low-k spin-on materials. Typically, two separate steps occur during the spin-on dielectric deposition process: the first is an application of an organosiloxane film to promote adhesion across the inorganic/organic interface created by the transition from the copper cap layer—typically silicon nitride, but researchers have proposed the use of silicon carbide—and the via-level ILD material. The adhesion promoter is a hybrid molecule engineered for reaction and subsequent bonding with the inorganic surface and the polymer ILD material. It also creates a highly uniform surface, independent of the underlying substrate and local topography. Approximately 50% of the physical footprint of the spin-track equipment is dedicated to performing this priming step, which accounts for about 40% of wafer processing time. Significant throughput and COO improvements could be achieved if the adhesion promoter was formulated within the spin-on dielectric solution. The number of coat-and-cure steps required per interconnect layer would be reduced, and additional cost savings would result from reductions in inventory, a decrease in the number of waste-stream components, and a reduction in waste-stream volume. Decreasing the required number of coat-and-cure steps per layer also can potentially reduce film defectivity and thereby enhance device yields. A comparative study was performed by researchers from Dow Chemical and IMEC at the IMEC research center in Leuven, Belgium, to evaluate the properties of self-primed materials versus conventional low-k dielectrics and the potential impact of eliminating the use of an adhesion promoter on integration process flows. The methods employed and the results of that study are described below. Experimental Procedures The study compared the use of a self-primed low-k dielectric material (SiLK J resin) applied in a single-step (spin-bake-cure) process and a conventional, non-self-primed low-k dielectric material (SiLK I resin) applied in a dual-step (spin-bake–spin-bake-cure) process within a copper single-damascene process flow. A simple process flow was chosen to isolate as much as possible the potential differences between the two formulations and deposition processes from the multitude of subsequent integration process steps. The two test resins are based on the same organic polymer and solvent system and have the same basic film properties, but the self-primed material contains a specially formulated additive that eliminates the need for a separate adhesion promoter. In addition, its single-step coat-and-cure process does not allow for additional planarization. Process Flow. Processing of the low-k dielectric materials was performed on an ACT 8 SOD spin-track from TEL (Tokyo/Austin, TX) with dispense volumes of 1.2 cm3 for each resin. Bake cycles were held constant at 200°C for 90 seconds for both materials, and both were exposed to a similar set of test cure-process parameters (temperature and time). Curing was accomplished in an A400 vertical furnace from ASM International (Phoenix). The application of the adhesion promoter (AP4000 from Dow Chemical) prior to the processing of the non-self-primed resin was performed in a separate spin-cup on the ACT 8 spin-track using a dispense volume of 2.5 cm3 and a bake process of 185°C for 60 seconds. The production of copper structures included creating the following stack: a 100-nm plasma-enhanced (PE) CVD silicon carbide substrate, a 500-nm SOD layer, and a 150-nm PECVD silicon dioxide cap. Etching of the single-damascene trench structures was accomplished with a single hard mask in a TCP9100 etcher from Lam Research (Fremont, CA), using an oxygen/nitrogen–based etch gas composition. The tantalum nitride barrier metal and copper seed layers were deposited using an Electra system from Applied Materials (Santa Clara, CA), electrochemically deposited copper plating was performed in an Equinox tool from Semitool (Kalispell, MT), and the chemical-mechanical polishing (CMP) process was performed on a Teres system from Lam Research. Cure Window. The focus of the comparative study was to evaluate the impact of various furnace cure temperatures, ranging from 400° to 470°C, on the electrical performance of the two dielectric films. The test vehicle was a single-damascene copper back-end-of-line (BEOL) structure using a lithographic DUV target of 250 nm. A multitude of test structures were available within each die, but this work concentrated on those structures designed to determine copper line continuity, the interline k-value of the dielectric materials, and interline leakage current. The copper line resistance and any effects related to the cure window for both resins were analyzed by evaluating the resistance of long critical-dimension (CD) lines, measured by a four-point resistance measurement technique. Dedicated fork comb structures and other specific structures allowed the evaluation of CMP efficacy as a function of the cure window and the resin used. Electrical Test Results The CD line resistance measurement results for the two dielectrics are shown in Figure 3. Two conclusions can be drawn from those data. First, there was an increase in resistance distribution when cure temperatures of 450°C or higher were used. This effect was most pronounced for the self-primed low-k dielectric material (Figure 3b). In contrast, the resistance distributions when cure temperatures were below 450°C were narrow and overlapped. Second, in the case of the self-primed film, the shift to higher resistance values was induced by a small change in etch profile that resulted in a smaller effective copper cross-sectional area of the line. This small increase can be attributed solely to a smaller CD, not to an incomplete etch process or roughening at the bottom of the trench structures. The scanning electron microscopy (SEM) image in Figure 4 reveals that there were no defects at the bottoms of the trenches, as would be expected, since the patterning was done in an oxygen/nitrogen–based etch chemistry.
An evaluation of an 18-mm-long meander line revealed that the cure temperature had no effect on line continuity. However, the choice of dielectric resin did have an impact, as shown in Figure 5. The slight overall increase in copper line resistance for the 18-mm-long meander test structures processed with the self-primed resin indicates that a small CD reduction was achieved. However, although some variation in copper line resistance was observed in these tests, device yields were not affected.
Because temperatures above 450°C are thermally challenging for organic polymer–based dielectrics, the stability of their k values at high temperatures is critical. It is also imperative that the k value of a self-primed version of such a material be identical to that of the version requiring a primer. The latter attribute is important so that when the switch to the new material is implemented, the system performance of current designs will not be affected, while the former attribute is necessary for ensuring continued product reliability. Figure 6 presents the interline capacitance for the non-self-primed and self-primed resins cured at two of the test temperatures, revealing that capacitance was independent of product choice within the cure window evaluated in this study. Conclusion The semiconductor industry's efforts to uphold Moore's Law and continue to decrease wafer COO can be advanced by substituting a self-primed low-k dielectric resin for conventional low-k materials that require the use of an adhesion promoter. The IMEC study discussed in this article found that a self-primed version of Dow Chemical's spin-on dielectric resin SiLK exhibited properties similar to those of the original when processed under the same conditions at cure temperatures up to 450°C. Acknowledgments The authors would like to thank Karen Maex, Serge Vanhaelemeersch, and their respective research divisions at IMEC, as well as the IMEC pilot line that processed the wafers. They would also like to thank Ken Foster and Jolee Dominowski of Dow Chemical for their support of this project. Reference 1. R Goldblatt et al., "A High Performance 0.13-µm Copper BEOL Technology with Low-k Dielectric," in Proceedings of the 2000 IITC (San Francisco: IEEE, 2000), 261–263. Joost J. Waeterloos, PhD, is a senior integration specialist for Dow Chemical (Midland, MI) and is currently an affiliated researcher at IMEC in Leuven, Belgium, performing research in the area of low-k interlayer dielectric materials. Before joining Dow three years ago, he was a researcher at IMEC investigating the area of low-k integration. Waeterloos has authored more than 20 publications and holds four patents. He received a PhD in microelectronics from the University of Leuven, focusing on the characterization and integration of low-k dielectrics. (Waeterloos can be reached at +32 16 281747 or jwaeterloos@dow.com). Michael E. Mills, PhD, is global applications development manager for the semiconductor fab materials division of Dow Chemical. Since joining the company in 1989, he has been involved in the research and development of several ceramic and polymer materials, including high-performance fiber and advanced materials for IC manufacturing. Mills has published numerous technical papers and is a committee member of the International Technology Roadmap for Semiconductors interconnect technology working group. He received a PhD in ceramic science and engineering from Rutgers University in Piscataway, NJ. (Mills can be reached at 989/636-9131 or memills@dow.com).
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Since
Gordon Moore first observed the doubling of integrated circuit performance
every 18 months, Moore's Law has been a roadmap for success in the semiconductor
industry. Chipmakers uphold the paradigm and devote significant efforts
to maintaining the tornadolike pace of development it requires, largely
because gains in performance have typically been accompanied by parallel
reductions in IC production costs, measured by the industry as wafer
cost of ownership (COO).
