MICRO: Improving the etch process as part of an overall plan to increase fab productivity

A project at a semiconductor fab shows that wafer yields can be increased by optimizing equipment productivity, production recipes, process-integration flow, and manufacturing methods.

Advances in manufacturing methods and fab organization are crucial to yield enhancement strategies in the semiconductor industry. Achieving such advances has been the goal of a productivity improvement project at Infineon Technologies (formerly White Oak Semiconductor) in Richmond, VA. Since the fab's founding in 1997, a continuous effort has been made to improve equipment and process technologies and optimize production methods to increase the fab's capacity.

Members of the project team have sought to significantly increase wafer starts per week using only the resources at hand (including the floor space of the existing cleanroom) while keeping capital investments to a minimum. The team's task has been to improve equipment productivity, optimize equipment utilization, and increase personnel effectiveness. As part of the company's effort to achieve fabwide productivity gains, the team has focused on one of the most challenging areas in the fab: the etch process. This article concentrates on those activities of the improvement team, which addressed several issues:

White Oak Semiconductor's Richmond fab ramped up at record speed when the first product was shipped in 1998. The facility was initially designed for 6000 wafer starts per week. However, because of competition in the DRAM market, it was important to continually seek to reduce manufacturing costs, and increasing wafer starts is one way to so that. A detailed study of the fab's potential capacity indicated that an increase in wafer starts per week was possible only by improving almost every facet of the manufacturing cycle. To accomplish this task, the productivity improvement team needed to overcome a series of constraints.

Facility Layout. One major constraint to improving productivity was the facility's fixed layout. Planning a fab's capacity is based on dedicating a particular type of tool to a particular process. Often it is difficult to rearrange equipment dedication after ramp-up. To circumvent this limitation, substantial increases in throughput can be achieved by combining chambers that perform fast and slow etch processes on a single equipment platform. Maximized equipment throughput can be achieved by rearranging chamber dedication or by using the same chamber for two or more processes.

A slow transfer-chamber robot can decrease the throughput of a multichamber platform. The faster the robot's movements, the higher the platform throughput. Fast robots are especially important in processes with short recipes. As recipe times increase, the robot remains idle longer. Consequently, the use of the robot is most effective when shorter and longer recipes are combined on the same platform. Higher throughput can be achieved by combining shorter and longer recipes on the same platform than by implementing individual recipes on two separate platforms, assuming that the single platform has the same number of chambers as the two separate platforms and that it uses two loadlocks in parallel-lot mode.

Product Mix. As a rule, the fab production line runs a mix of several products. The difference between products is defined by the ground rules of applied technologies and by the commercial purposes of the manufactured ICs. Experience shows that more dedicated tools and longer etch recipes are required for products with smaller geometries. This constraint makes it difficult to plan a fab's capacity for the next product generation and forces engineers to make continual adjustments to throughput projections.

Production Line Ramp-Up. The fast pace of introducing new product greatly shortens the time between the development stage of a new process and its production implementation. In many cases, therefore, the final tweaking of a process occurs under real manufacturing conditions. Accordingly, complications related to volume production frequently are revealed only under real volume-production conditions, making it necessary to redevelop processes or perform additional chamber seasoning and cleaning. As a result, capacity is often reduced.

Capital Expenditures, Capital Efficiency, and Resources. The force that drives an increase in wafer starts—increasing the fab's profitability—also limits capital expenditures. Capital expenditures can be justified only if they promote productivity. There is no economic reason to buy new equipment or upgrade existing equipment if such activities do not result in increased profits, or if the return on investment is delayed substantially. By the same token, resources can be dedicated to process and equipment optimization only if the benefits of optimizing are not unduly delayed.

The improvement in equipment productivity was achieved in three stages. The first stage was dedicated to the optimization of a single selected equipment set to achieve maximum wafer throughput. During the second stage, the achieved optimized equipment settings were transferred to other, similar tool sets. Process performance was carefully controlled, and no deviation from the established process output was permitted. Finally, during the third stage, a set of procedures was established to freeze the equipment status at the optimized state. These procedures are required to ensure that the key equipment parameters continue to be maintained at the established optimized level.

Figure 1 contains a checklist of equipment parameter optimizations for an etch tool. The settings appearing in the chart enabled the fastest wafer-transfer times on a single platform. After the desired improvements had been achieved, the experimental tool was used in volume production to verify that the changes had no negative effect on product performance. The optimized tool set performed the same or better than it had prior to optimization, with significantly improved lot-processing time.

In the next stage of the project, all of the tools were inspected and identified differences were documented. Using checklists for every platform, optimal settings were applied to identical tools. A systematic approach to each tool and proper documentation procedures enabled the project team to standardize high-throughput equipment performance.

As part of the overall improvement of the etch area, the project team optimized the "mechanical" aspects of the production recipes, including plasma striking, gas-flow stabilization, pumpdown, and ventilation steps. Throughput can also be increased by improving the "processing" part of the recipes, which requires that the recipes be requalified.

A typical production recipe consists of a stabilization step and one or several processing steps. In addition, processing steps may be separated by additional stabilization steps. Reducing stabilization time is one of the largest contributors to throughput improvement. A stabilization step helps to achieve a balance between the flow of an etching gas mixture and chamber pressure. No power is applied during this step. Stabilization conditions are controlled by a variety of parameters, such as pressure in spec, flow in spec, and time. Throttle-valve presets also play an important role in stabilizing pressure. The throttle-valve preset parameter can be selected in the recipe header.

Figure 2 illustrates how the project team decreased stabilization time. While in Figure 2a the throttle valve was not preset, initiating automated stabilization from the 0 position, in Figure 2b the throttle valve was preset from the recipe header at an average processing position. After the throttle valve's preset starting position was selected, stabilization time was reduced from 10 to 3 seconds. This 7-second reduction in stabilization time helped to reduce a typical multistep production recipe by 20 to 30 seconds, resulting in a significant overall improvement in throughput. Other parameter settings that influence recipe overhead time are shown in Figure 3.

As in the case of the equipment optimization procedure, the recipe optimization was passed on to all the tool sets performing similar etch processes. To accomplish this task, proper documentation helped to ensure continuous control of the optimized parameters. During all phases of the improvement project, a systematic approach and careful documentation procedures ensured that a simultaneous and successful transition of many identical chambers to a standardized high-throughput mode could be achieved.

In this project, optimizing process integration was limited to those processing steps that required improvement. The work focused on two approaches: optimizing etch process output (e.g., accelerating processing without deteriorating process outputs) and modifying product integration in order to reduce overall processing time.

Figure 4: Schematic showing that total processing time can be decreased when the planar etch step is performed by a faster, less-selective process and the in-trench step is performed by a slower, more-selective process.

Figure 4 illustrates how process acceleration was achieved. The final goal of this hypothetical etch process is to remove material A from the top of material B, clean trenches, and stop precisely at the bottom of the trenches. Total processing time was decreased substantially when the planar etch step was performed by a faster, less-selective etch process, while in the final stage a slower, more-selective in-trench process was applied to provide better control. As shown in Table I, the proper timing of these two steps helped to reduce total processing time from 130 to 100 seconds, which yields a 23% improvement in process throughput.

Processing Method/ Etch Rate	Processing Time
Processing Method/ Etch Rate	Stability 1	Planar Etch	Stability 2	In-Trench Etch	Total Time
Single-step etch	6 sec	60 sec	4 sec	60 sec	130 sec
Single-step etch rate	—	300 nm/min	—	300 nm/min	—
Two-step etch	6 sec	40 sec	4 sec	50 sec	100 sec
Two-step etch rate	—	600 nm/min	—	300 nm/min	—
Table I: Total processing time can be reduced by splitting etch steps into two processes: fast planar etch and slow, highly selective in-trench etch.

Improving Equipment Availability

The productivity of the etch area can be greatly increased by improving equipment availability. The traditional approaches to expanding equipment availability include extending wet-clean cycles, expanding the life span of equipment process kits, and implementing new chamber-cleaning procedures, such as dry cleans. The use of these traditional methods is an ongoing process and a routine responsibility of process and equipment engineers.

Nontraditional approaches to improving equipment productivity include shortening equipment qualification procedures or replacing such qualifications altogether with on-product measurements. Such methods can be implemented in the case of the nitride spacer etch, which is widely used in semiconductor manufacturing. In that process, a layer of deposited material is etched away to provide isolation between gate conductor structures. However, the etch must stop at the underlying gate oxide layer, which is achieved by using an optical end-point signal. Traditional qualification of the spacer etch tool includes periodic etch rate (ER) verification, which is accomplished by performing a timed etch step on a blanket wafer followed by pre- and postetch thickness measurements. Collected using statistical process control software, these data are routinely received by a process engineer.

Figure 5: Comparison between (a) traditional blanket wafer etch rate SPC data and (b) end-point time SPC data, in which the data points are histograms of end-point times.

That multistep procedure can be bypassed by controlling the tool's etching rate either through statistical process control of the collected end-point times, as shown in Figure 5, or through etch-rate data that are calculated from the end-point times and incoming thickness measurements. These end-point time and thickness measurement data are collected from the product routinely. In general, the thickness of the etched layer is measured at the deposition step and can be used as an input parameter for the ER calculation.

At the same time, the wafer-disposition procedures were revised. Traditionally, a series of steps are followed when equipment breaks down: wafer processing is stopped, proper documentation (a processing discrepancy document, or PDD) is filed describing the event, trapped wafers are recovered from the tool, and the metrology measurements required to confirm that no damage was done to the product as a result of the event are performed. The improvement project demonstrated that the final metrology step is centrally responsible for the delays that occur in the dispositioning of faulted lots. Such delays may last from a few hours to several days.

During the project, all PDD-listed wafers processed in the etch area in the course of a weeklong experiment (80 PDDs involving a total of 130 wafers) were traced to the back end of the line. Figure 6 presents examples of these PDD events. After the affected wafers were traced through the production line, the product yield from these wafers was evaluated and compared with an average yield for the selected period. The experiment showed that none of the wafers had to be scrapped at the end of the line; only 9 out of 80 wafers deviated from the average yield (deviations ranged from 1–2% to 10–15%). However, the time lost for recovery, inspections, and additional measurements totaled approximately 400 hours.

These results indicated that such an insignificant yield loss does not justify expending tremendous effort and consuming sizable resources to recover wafers and perform additional metrology measurements. At the conclusion of the experiment, it was decided to modify the wafer-disposition procedures for less-critical processing steps. If the nature of an event is not very critical (e.g., a backside helium fault or a stabilization fault in a mass-flow controller), the area sustainer must file a PDD describing the event and then resume processing. At the end of the line, all single low-yielding wafers are compared to documented PDDs, which are used as the basis for determining the wafers' final dispositioning.

The etch productivity improvement project focused on optimizing five major areas of work: equipment productivity, etch-recipe overhead, processs-integration flow to achieve shorter cycle times, equipment availability, and manufacturing methods and procedures. The results exceeded initial expectations. Equipment and recipe throughput alone increased by an average of 16% for all etch-area cluster tools, and in some cases, throughput increased from 60 to 70%, decreasing the need to purchase additional platforms.

Successful collaboration by cross-functional teams substantially improved equipment availability, throughput, and utilization. The implementation of the findings is continuing, and the lessons of the etch project are being applied in other fab areas. This continuing effort will make it possible for the fab to achieve a significant increase in wafer starts per week without having to expand cleanroom floor space and make large capital outlays.

The author would like to thank Sandro Pampel and Jeorg Domaschke from Infineon Technologies in Dresden, Germany, for providing data for the equipment optimization part of the project. Additional thanks go to Peter Gilgunn of Infineon Technologies in Richmond, VA, for numerous discussions and inspiration. The author would also like to thank Chris Eaton, Ken Chernesky, Marcel Gaudet, Fergus Butler, and Kevin Brann of Applied Materials (Santa Clara, CA) for their contributions to the equipment and recipe optimizations. Finally, the author would like to acknowledge Tom Occhino, Mark Sizemore, Kay Dittmar, Cathy Odor, Daryl Cook, Mark Curtice, Megan Karras, Semyon Libon, Myrtle Humphreys, and Richard McNeill of Infineon Technologies, Richmond, whose team efforts made this project possible.

Yuri Karzhavin, PhD, is a manager of the advanced process control project at Infineon Technologies in Richmond, VA. He joined White Oak Semiconductor in 1997, working as an etch group leader in the department for new product introduction and as a productivity improvement project leader. Before that, Karzhavin worked at Motorola's Advanced Product Research and Development Laboratory (Austin, TX), specializing in advanced logic technology development and manufacturing, as well as on dry-etch processes, plasma-induced charging, and device damage. The author or coauthor of more than 36 papers, he holds two patents. He received a PhD in plasma physics from Moscow State University and an MBA from Virginia Commonwealth University in Richmond. (Karzhavin can be reached at 804/952-7670 or yuri.karzhavin@infineon.com.)

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