Investigating and eliminating sphere defects in T1 and T2 technologies

Fourmun Lee, Myn Newtran, and Terry Hulseweh, Motorola

In a fab study, defect density monitoring identified defects in new technology processes, leading to the use of an RF mode and e-chuck operating voltage that eliminate the defects and optimize yields.

The successful development and implementation of new device technologies requires the optimization of all parameters that can have a negative impact on final device yields. Key areas of focus are transistor performance characteristics, device module integration, process integration, and process-induced defects. The performance of the manufacturing process in each of these areas determines the overall manufacturability of the product. As device geometries shrink, understanding and minimizing process-induced defects is critical to achieving and maintaining high device yields.

This article describes some of the defect reduction activities performed at Motorola's MOS 12 die manufacturing facility in Chandler, AZ, during the evaluation of two new device technologies: T1 and T2. The article discusses the experiments that were performed to identify a defect source and determine the mechanism of defect formation. In addition, the steps that were implemented to eliminate the defect issue are presented.

Identifying T1 and T2 Defects

The methods commonly used to measure the performance of a fab or process are electrical defect density and process defect density analysis. Electrical defect density is determined from the end-of-line probe yield and encompasses all phases of device manufacturing. If the device exhibits parametric sensitivities (e.g., a narrow Leff window because of marginal design), performing electrical defect density analysis will not accurately reflect the true performance of the manufacturing line. In contrast, process defect density, which is typically monitored in real time, provides a better measure of the defect performance of process tools and recipes. All modern fabs monitor defect performance through in-line inspection of product as it is being processed through the fab. While inspection strategies vary somewhat from fab to fab, inspections are typically performed at the end of critical process modules using tools that are readily available in the industry.

During the initial development of the T1 and T2 processes, defect density analyses detected intermittently high levels of defects in the isolation module. Although T1 is not a trench-based isolation technology, as is T2, and the process chambers and recipes used for the T1 etch process are significantly different from those of T2, scanning electron microscope (SEM) characterization indicated that the T1 and T2 defects were about the same size and had the same circular appearance as one another. As illustrated in Figure 1, an SEM image generated during defect characterization, the defects were circular islands of unetched silicon covered with full-thickness nitride that appeared as extra, unwanted patterns in the device. Because of the nature of the defects, the etch tool was considered the most likely cause of the problem. Whenever a defect excursion was detected, the tool was taken down for an investigative wet clean and the replacement of suspect components. However, when the tool was returned to service, the problem reappeared after a few wafers or lots had been processed.

Figure 1: SEM micrograph of a circular isolation module defect.

At some defect locations on the wafer surface, sphere particles were found in the vicinity of the pattern defects. Figure 2 is an SEM micrograph of a typical T1 etch-pattern isolation defect with an accompanying particle that caused micromasking, and Figure 3 is an SEM micrograph of a typical T2 trench defect with its accompanying particle.

 

Figure 2: SEM micrograph of a typical T1 isolation defect with an accompanying particle that caused micromasking.

Figure 3: SEM micrograph of a typical T2 trench defect with an accompanying particle that caused micromasking.

The characterization of isolation defects over time revealed that the extent of the defect problem varied greatly from lot to lot and even from wafer to wafer. All of the defects appeared as point defects in the optical review process. SEM analysis indicated that these point defects were typically 0.3–0.5-µm pattern defects, although some larger defects were detected in the 2-µm range.

As illustrated in the energy-dispersive spectroscopy (EDS) spectra in Figure 4, the spheres contained aluminum, raising concerns that metal could contaminate front-end wafers and process tools. In the course of investigating the defect mechanism, additional evidence of aluminum-containing defects was collected. Figure 5, a micrograph of an aluminum defect, shows that aluminum spheres were often significantly larger than 0.5 µm in size. Moreover, aluminum defects were not necessarily spherical, as illustrated in the micrograph in Figure 6.

Figure 4: EDS spectra of a sphere defect indicating the strong presence of aluminum.

Figure 5: SEM micrograph of an aluminum defect.

Figure 6: SEM micrograph of a nonspherical aluminum defect.

Isolating the Defect Source

Process partitioning studies performed on material from the T1 and T2 isolation modules confirmed that the etch process generated the defects. The isolation etch step for both processes is performed on the same tool platform. However, whereas the etch process for the T1 technology is performed in a single chamber, the T2 technology uses a two-chamber etch process, whereby the hard-mask etch is performed in one chamber and the trench etch is performed in the other. An isolation experiment confirmed that the tool used for the T2 technology had a defect count per wafer of 287, while the tool used for the T1 technology had a defect count per wafer of 21.

In the T1 process, the defects were first detected after reactive ion etch (RIE) of the nitride/oxide stack and appeared as full-thickness circular pattern defects. In the T2 process, the defects were formed in the hard-mask portion of the RIE etch (also a nitride/oxide stack). These defects were subsequently transformed into trench defects having a conelike appearance when the hard-mask pattern was transferred into the underlying silicon.

Examinations of the process chambers following defect excursions typically revealed nothing unusual except occasional dark spots on the electrostatic chuck (e-chuck). That observation and the defect characterization data suggested that the most likely cause of the defect problem was microarcing during processing. Since etch is a multistep process even when a single process chamber is used, it was essential to determine when microarcing occurred and the process parameters that drove this undesirable event. Knowing the tool platform, engineers identified RF mode, gas flow, chamber pressure, and pumping sequence as the key parameters. Experiments were designed around these parameters, with defect density as the response variable. Process parameters that were expected to affect the process output, such as critical dimension, trench profile, and trench depth, were intentionally kept fixed.

Four sets of diagnostic studies were performed on the four process parameters. The first set of tests was designed to understand the system's behavior when the last plasma step in an etch recipe is followed by a pump step. When the last etch step is followed by a pump step in back-to-back (B-to-B) mode, the pump step requires that gas flow and pressure return to zero while the RF power ramps down to zero. This procedure can cause unstable plasma conditions, since all gases, pressure, and RF power change at the same time. The situation is most severe when the RF ramp-down rate is slow, leaving significant residual RF power when all gases have been shut off and the throttle valve is fully open. Depending on the RF ramp-down rate, this condition can potentially cause charged particles suspended in the plasma to collapse onto the wafer surface.

The second set of tests investigated system behavior when a plasma step is followed by a stabilization step. If the gas flow and pressure regime between the etch and the stabilization steps are significantly different, an unstable plasma condition can result during RF ramp-down and microarcing can occur at the edge of the e-chuck.

The third set of tests analyzed operating behavior when a plasma step is not followed by a stabilization step. When etch 1 and etch 2 follow similar process regimes, the B-to-B mode provides a smooth transition between the two steps without RF power ramping down and then up. However, if the etch step conditions are significantly different, e-chuck microarcing can occur when gas flow, pressure, and RF power settings are changed simultaneously.

The fourth set of tests investigated the operating behavior of the last process step with and without a pump step. When a plasma step is followed by a nonplasma pump step, gas flow and pressure return to zero while the RF power ramps down to zero, causing an unstable plasma condition. When the last step of the recipe is a plasma step, regardless of RF setting, the RF ramps down while the gas and pressure stay constant at their set points to prevent the formation of an unstable plasma.

Based on these studies, the mechanism by which defects were generated in the isolation etch module could be determined. After wafers were loaded in the etch chamber for processing, microarcing occurred during the initial RF ramp because of the high potential difference (DV) between the e-chuck and the process chamber. The microarcing caused molten balls of aluminum to form. When the aluminum solidified while suspended in the plasma, spheres formed, some of which fell on the wafer being processed, causing micromasking defects in the hard mask. Molten aluminum solidified on contact with the wafer surface, forming a teardrop-shaped particle. Pattern defects were generated as a result of micromasking by the aluminum defects. At the same time, additional particles suspended in the plasma collapsed onto the wafer surface because improper RF modes were used in the etch recipes. During subsequent trench etch steps, many trench defects were generated because of the micromasking caused by aluminum defects and the particles resulting from the improper use of RF modes.

Experimental Results

The four sets of studies enabled a detailed understanding of the system's reaction to parameter changes. However, while this characterization work showed that optimizing the output for a new process is necessary, such output optimization is insufficient for establishing a new manufacturing process. A thorough understanding of system interactions is also required to optimize defect density response.

The studies indicated that the use of an improper RF mode during etch causes the plasma to "slam," collapsing the suspending particles onto the wafer. This response is demonstrated by the RF-on particle testing data shown in Figure 7. Whereas the first part of the chart indicates that particle counts were high and erratic when the system was running with the improper RF mode, defect performance improved dramatically when the correct RF mode was used, as quantified in Table I.

 

Figure 7: RF-on particle data showing defect performance of the trench etch process before and after the process recipe's RF mode was modified.

Process RF Defect Recipe Mode Count Standard B-to-B 559 Modified RF-off 46

Table I: Defect performance improved dramatically when the correct RF mode was used.

The choice of process recipe and RF mode has a great effect on the mechanism and sequence of gas flow, pressure, and RF power from one process step to another. When the system is configured for B-to-B RF steps without intervening restabilization, RF-off mode should be used in each plasma step that is followed by a stabilization or a pump step; B-to-B mode should be used between two similar plasma steps to ensure a smooth transition; and RF-off mode should be used between two plasma steps performed under different process conditions.

In addition to the interactions that were observed during the four sets of studies, high defect conditions can result from microarcing between the e-chuck and the wafer. This undesired interaction generates spherical aluminum particles that can be deposited on the wafer and cause micromasking defects. Microarcing weakens the anodization on the e-chuck and renders it more susceptible to subsequent arcing. To eliminate microarcing, e-chucks that have been affected by microarcing should be replaced, the e-chuck operating voltage should be lowered, an autobias hardware upgrade kit should be used to minimize the DV during RF ramp, and the e-chuck voltage should be activated before the plasma is turned on.

Figure 8 demonstrates the dramatic improvement in the defect density of the trench etch process after the equipment and process fixes described in this investigation were implemented. These data were collected on product during the early product development cycle.

Figure 8: In-line inspection data showing defect performance of the trench etch process before and after the implementation of equipment and process fixes.

Conclusion

A defect issue identified by in-line defect monitoring in the isolation etch modules during the development of T1 and T2 technologies was potentially a major contributor to wafer scrap, yield loss, and process-tool downtime. Fortunately, the issue was resolved prior to product qualification and production ramp-up by determining that it was caused by the microarcing of the e-chuck in one type of etch chamber. The microarcing generated aluminum-containing particles that fell on the wafer, causing micromasking. The problem was solved by lowering the e-chuck voltage, implementing an autobias hardware upgrade that minimized the voltage difference between the wafer and the e-chuck, using the correct RF mode in all process recipe steps, and enabling the system to turn on the e-chuck voltage before the plasma is turned on. Thus, the defect problem was solved through the institution of the electrostatic chuck best-known-methods approach.

By implementing these process changes, sphere defects were eliminated from the T1 and T2 processes, resulting in a three- to fivefold reduction in T1 isolation module defects and more than a tenfold reduction in T2 defects. At the same time, tool uptime was increased, process cycle times decreased, and the need to replace e-chucks fell dramatically. (Before these process changes were implemented, e-chuck lifetime was 1 to 2 weeks, while afterwards it increased to tens of weeks.) Consequently, tool availability increased by 10% because the interval between wet cleans was increased, costs for parts per tool per year were lowered significantly, and unit probe yield increased. Data are being gathered on the new baseline defectivity level in the quest to further improve yields and optimize tool maintenance.

Acknowledgments

This article is based on a presentation given at the IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop held in Boston September 12–14, 2000. Used with permission. The authors would like to thank Tom Foster of Applied Materials (Santa Clara, CA) for his work on the project discussed here. They also wish to acknowledge the contributions of members of the device engineering department, etch-equipment maintenance department, and analytical lab at Motorola's MOS 12 fab.

Fourmun Lee, PhD, is a senior principal staff scientist at Motorola's MOS 12 manufacturing site in Chandler, AZ. He has 12 years of experience in the fields of semiconductor process development and yield enhancement. Currently he is focusing on module integration and yield enhancement in silicon device manufacturing. Lee has published 30 technical papers and holds three patents. He received a BS in chemical engineering and materials science from the University of California, Berkeley, and an MS and a PhD in chemical engineering from the University of Illinois in Champagne-Urbana. (Lee can be reached at 480/814-3635 or rxjp50@email.sps.mot.com.)

Mynn Newtran was a senior staff engineer in the plasma etch area of Motorola's MOS 12. He has 15 years of experience in plasma etch processing. His recent work has focused on trench etch process development and optimization.

Terry Hulseweh is a senior staff engineer at Motorola's MOS 12 facility. He has 32 years of experience in semiconductor process and device characterization. Presently he is working on new technology development and process integration. Hulseweh has authored 10 technical papers and 5 defensive publications. He holds seven patents. He received a BS in physics from Arizona State University in Tempe. (Hulseweh can be reached at 480/814-3127 or rbb450@email.sps.mot.com.)

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