CONFERENCE PROGRAMS

The following list includes technical and business program events to be held during the week of Semicon Europa 2001. The sessions take place at the International Congress Center Munich (ICM) in the Trade Fair Center unless otherwise noted. For more information and the latest updates, log onto http://www.semi.org.

MONDAY, APRIL 23

8:30 a.m.–7:00 p.m.

The 12th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC) 2001 (cosponsored by SEMI, IEEE, and MICRO)

Technical Chair: Mart Graef, Philips Research

Best Paper Award 2000 ASMC—sponsored by DuPont Photomasks, "Maximizing Profitability Through Easy Information Transfer"

Charles Weber and Eric von Hippel, MIT Sloan School of Management

Session I: Factory Dynamics 1 (sponsored by Entegris)

Chairs: Thomas Kaufmann, Fraunhofer Institute IPA; and Javier Bonal,
Agere Systems

Invited Paper: Quantifying Operational Time Variability: The Missing Parameter for Cycle Time Reduction

J. H. Jacobs, L. F. P. Etman; J. E. Rooda, Eindhoven University of Technology;
E. J. J. van Campen, Philips Semiconductors

A Statistical Approach to Cycle Time Management

J. Bonal, M. Fernández, O. Maire-Richard, S. Aparicio, R. Oliva, L. Rodriguez, and M. Rosendo, Agere Systems

Cost Reduction Using Systematic Target Setting of the Reference Fab Methodology

Ralf Plieninger, Werner Reczek, Urs Müller, Hans Ehm, Ralf Jetzfellner, Alexander Trost, and Haron Azlan, Infineon Technologies

How Differentiating Between Utilization of Effective Availability and Utilization of Effective Capacity Leads to a Better Understanding of Performance Metrics

John Matthews and Kristin Butler, IBM Microelectronics

Balancing Mask and Photolithography Costs

Jeffrey P. Bonn, Sharon Sisler, and Pat Tivnan, IBM Microelectronics

Determining the Capacity Components of Different Classes of Multi-Chamber Tools

Karen Connerney, Don Martin,
IBM Microelectronics;
Ryan Tomka, Tefen USA

Session II: Process Control

Chairs: Winfried Meier, Nikon Precision Europe; and Terry Leslie, Dominion Semiconductor

Invited Paper: Automated Photolithography Critical Dimension Controls in a Complex, Mixed Technology Manufacturing Fab

Craig Schneider, Andrew Watts, and John Smyth, IBM Microelectronics

Process Control Strategy Based upon Device Performance Metrics

Steven Ruegsegger and Brian Conchieri, IBM Microelectronics

Advanced Process Control, Functionality Requirements for Lithography Process

Christopher J. Gould, Infineon Technologies

In Situ Plasma Etch Process Endpoint Control in Integrated Circuit Manufacturing

Thomas Reis, Luxtron

Session III: Advanced Process Technology

Chairs: John Goodman, Entegris; and Yuri Karzhavin, Infineon Technologies Richmond

Invited Paper: Manufacturing Optimization of Shallow Trench Isolation for Advanced CMOS Logic Technology

Tony Speranza, Y. Wu, J. Wong, E. Fisch, J. Slinkman, and K. Beyer,
IBM Microelectronics

Modular Silicon-on-Insulator Process for Power Devices and Power Integrated Circuits

René P. Zingg and Rob Bonne, Philips Semiconductors

New Process Flow for Combined Three-Layer and Self-Aligned Contacts

Gerhard Spitzlsperger and Masato Sadaoka, Hitachi Semiconductor Europe; Masahiro Shioya, Hitachi ULSI

Studies of ZrO₂ and HfO₂ Deposited by Liquid Source Misted Chemical Deposition in MOS Gate Structures

Jerzy Ruzyllo, D. O. Lee, P. Roman, and M. Horn, Penn State University; P. Mumbauer and R. Grant, Primaxx

Session IV: Poster Session (sponsored by KLA-Tencor)

Chairs: James Dougan, Motorola; Scott McClure, IBM Microelectronics; Rob Pearson, Virginia Commonwealth University; Larg Weiland, PDF Solutions

Capacity Analysis Tool

Sharon Sisler, Edward Merrill, and Philip Sorrentino, IBM Microelectronics

A Practical PZT Dry Etching Process That Increases the Top Electrode Contact Reliability in Pyroelectric Detector Arrays by Using a M0RI High-Density Plasma System

Dave Thomas, Y. P. Song, and K. Powell, Trikon Technologies; R. Bruchhaus, Siemens Corporate Technology

A Hard Mask STI Process for 0.13-µm Geometry and Beyond Logic Technologies

Justin Wong, Chip Whiting, Jim Hart III, and James Weil, IBM Microelectronics; George Matteson, Masaaki Hagihara, and Hiromasa Mochiki, Tokyo Electron America

Raman Spectroscopy, High-Pressure Phosphine Anneal and the Electrical Properties of the DRAM Capacitor

Sam Sawaya and Mohamed el-Hamdi, Samsung Austin Semiconductor

Long Throw and i-PVD Liners for W-plug Via Applications

Steve Burgess, Keith Buchanan, and David Butler, Trikon Technologies; N. Urbansky and Sven Schmidbauer, Infineon Technologies

Enhanced Self-Aligned (SAC) Etch Stop Window by Using C₄F₆ Chemistry

Judy Wang, Bryan Pu, Ji Ding, Takehiko Komatsu, and Joon Moon Kim, Applied Materials

On Extensive Pump Handling of Chemical-Mechanical Polishing Slurries

Rakesh K. Singh and Benjamin R. Roberts, BOC Edwards

Is Your Gas Filter as Clean as You Think? Evaluation of UHP Gas Filters of Differing Membrane Types for Contamination Contribution

Armando Colorado and Kareem Vakhshoori, Millipore

Study for Cross-Contamination Between CMOS Image Sensor and IC Product

Chih-Hsing Chen, Hung-Jen Tsai, Kwo-Shu Huang, and Hsien-Tsong Liu, TSMC

Thickness and Density Measurement for New Materials with Combined X-ray Technique

Shinichi Terada, Hiroyuki Murakami, Hiroaki Furukawa, and Kazuo Nishihagi, Technos

Achieving Good Correlation Results Between Bitmap and Tencor Data

Miguel A. Merino et al., Agere Systems

Equipment Interface: The Heart of APC

Curtis Doss, International Sematech (AMD assignee); Chris Stewart, AMD

Noncontact Wafer Handling Using High-Intensity Ultrasonics

Josef Zimmermann, Gunther Reinhart, and Jürgen Hoeppner, Institute for Machine Tools and Industrial Management

Chemical Supplier Quality Management: The Changes and Challenges

Jim O'Brien, Dominion Semiconductor

9:00 a.m.–5:00 p.m.

Imaging Technologies Conference

Session I: Tools and Process Toward the New-Generation Lithography

Chair: Carmelo Romeo, STMicroelectronics

Status of 193-nm Lithography for Sub-0.13-µm Technologies: Performance and Issues

Benedict Mortini, STMicroelectronics

ArF Lithography Options for the 100-nm Technology Node

Geert Vandenberghe, IMEC

Consequences of ITRS Roadmap Acceleration for Device Makers on Advanced Lithography Integration into Development and Release of Technology

Jan-Willem Gemmink, Philips Semiconductors

Prospects for a Functioning Resist for 157-nm Lithography

Eugene D. Feit, International Sematech

A Current Assessment of NGL Technology Developments (an International Sematech view)

Phil Seidel, International Sematech

Illumination Selection for Dimension Control in Advanced Imaging Systems

Martin McCallum, Nikon Precision

Session II: Mask Machining and Enhancement

Chair: Gerd Unger, Infineon Technologies

Technology Acceleration—The Mask Factor

Walter J. Trybula, International Sematech

Progress Report on the Micronic Sigma Pattern Generator

Torbjörn Sandström, Micronic Laser Systems

Qualification of Reticles for Optical Enhancement Techniques

Wilhelm Maurer, KLA-Tencor

Balancing Alternating PSM (Simulations and Printing Results)

Uwe A. Griesinger, Infineon Technologies

Masks for Next-Generation Lithographies

Abrect Ehrmann, Infineon Technologies

Evaluation of Optical Proximity Correction (OPC) Depending on Mask Process and Development of Mask Error Correction Module

Alexandra Barberet, DuPont Photomasks

9:00 a.m.–6:00 p.m.

Third European Manufacturing Test Conference

Conference Committee: Ulrich Schoettmer, Agilent Technologies; Joachim Saehn, Infineon Technologies; Rene Segers, Philips Semiconductors; Roberto Toscani, STMicroelectronics

Opening Remarks

Walter O. Roessger, VP, SEMI Europe

Keynote Address

Current and Future Trends in SOC/SOP Product Development for Our Communication World

Speaker TBA

Morning Plenary Session: Enabling Technologies and Methodologies for the Cost/Efficient SOC/SOP Manufacturing Test

Chair: U. Schoettmer, Agilent Technologies

Application of Analog BIST Techniques for Telecommunication Devices

Jon Turino, Fluence Technology

Concurrent Testing—A Breakthrough to Cost Reduction

Martin Fischer, Agilent Technologies

Design Approach with Board Test/System Bring-Up in Mind

Jürgen Hilsberg, IBM Microelectronics

Panel Introduction Paper

Challenges and Opportunities of the ITRS Technology Roadmap for the Semiconductor Manufacturing Test

Peter Muhmenthaler, Infineon Technologies; Rene Segers, Philips Semiconductors

Morning Panel Session—What Is the Reality of the ITRS Technology Roadmap?

Chair: Rene Segers, Philips Semiconductors

Afternoon Plenary Session—Manufacturing Test Cell Efficiency/Economical Test Solutions

Chair: Joachim Saehn, Infineon Technologies

SerDes Testing High-Speed Instrumentation

Petra Georg, Teradyne

Wafer-Level Burn-In and Test

Carl Buck, AEHR Test Systems

Low-Cost, High-Productivity "Test Cell" Through Panel Test

Robert C. Keus, Teradyne Integra Test

Single-Insertion Multiple-Temperature Testing

Kevin McFadden, Schlumberger

Production Test of RFID Devices Used in Contactless Smart-Card Applications

Martin Stadler, Teradyne

Modeling and Empirical Techniques for Analysis of Test Cell Efficiency in a Multisite RF Environment

Jim Dawdy, Agilent Technologies

Panel Introduction Paper

Challenges for the Efficient Future Managing of the Semiconductor Manufacturing
Test Floor

Gene Gretchen, VP and Managing Director, STMicroelectronics, Malta

Afternoon Panel Session: Challenges in Successful IC Manufacturing Test

"Who Should Own the Manufacturing Test Floor?"

Chair: Ron Leckie, Infrastructure

9:00 a.m.–6:30 p.m.

International MEMS/MST Industry Forum

Chair: Uwe Behringer, Institute of Microstructure Technology, FZK

Cochairs: Henning Wicht, WTC-Wicht Technology Consulting; Steve Walsh, University of New Mexico; Job Elders, TMP

Session I: MEMS/MST Worldwide Strategy

Keynote Address: How to Put Innovation in Particular MEMS/MST Technology in Production

Dirk Beernaert, Head of Unit European Commission DG "Information Society"

Intelligent Micromachines: Opportunities and Challenges of the Next Silicon Revolution

Al Romig, Sandia National Laboratories

MEMS Activities in Tohoku University and in Asia

Masayoshi Esashi, New Industry Creation Hatchery Center (NICHe)

Session II: News from Europe

Chair: Henning Wicht, WTC-Wicht Technology Consulting

The Update of the Nexus MST Market Study 2000–2005

Reiner Wechsung, Steag Microparts

The Centre of Micro and Nanotechnologies—A Worldwide Initiative of Grenoble

Constant Axelrad, CEA-Grenoble

Match-X: Modular MEM; Packaging and Interface

Mathias Schuenemann, VDI/VDE-IT

Session III: MEMS/MST Technology

Chair: Steve Walsh, University of New Mexico

Microsystem in Hard Disk Drives

Ruediger Berger, IBM SSD

MEMS Technology for Automotive Applications

Jan Peter Stadler, Bosch

Electrical Biochips—A New Class of MST Devices

Anton Heuberger, ISiT

Session IV: Equipment

Chair: Job Elders, TMP

MEMS/MST Equipment and Application

Elmar Cullmann, Karl Süss MicroTec

Polymer Microfabrication on an Industrial Level: Challenges and Vision

Holger Becker, Jenoptik

Capability for MEMS Advanced Processing

Jay N. Sasserath, Unaxis

Session V: Foundries

Chair: Jiri Marek, Bosch

The Role of a Vertical Integrated Solution Provider in the Emerging MEMS/MST Market

Juergen Becker, StandardMEMS

The Role of Design Houses and Their Interface to MEMS Foundries

Sean Neylon, Colibri-CSEM

Session VI: Roundtable Discussion

Chair: Ron Lawes, Rutherford Application Laboratory

TUESDAY, APRIL 24

8:30 a.m.–5:00 p.m.

ASMC (Day 2)

Keynote Address: Capital and Equipment Spending Update: 2001—A Self-Fulfilling Prophecy

Klaus-Dieter Rinnen, Chief Analyst and Director, Dataquest/Gartner Group

Session V: Yield Modeling and Analysis I

Chairs: William Miller, IBM Microelectronics; and Sebastian Muriel, Agere Systems

Invited Paper: Swampfinder

Daniel Maynard, Bette Bergman Reuter, and Raymond Rosner, IBM Microelectronics

The Application and Validation of a New Robust Windowing Method—
The Poisson Yield Method

Rick E. Langford, Agere Systems Singapore; Juin J. Liou, University of Central Florida; Venkat Raghavan, Agere Systems

Random Defect Limited Yield Modeling Using a Deterministic Yield Model

Anthony Singh and Jon Rosin, Dominion Semiconductor

Field Test Results for an Automated Image Retrieval System

Kenneth W. Tobin, Oak Ridge National Laboratory

In-Line SEM Inspection for Yield Learning in Manufacturing Fabricator

Wanda Tomlinson, IBM Microelectronics; and Keith Bartholomew, KLA-Tencor

Improvement of Yield Enhancement Methods Due to AIT-II and Impact ADC 2.0 Capabilities

Kathleen Terryll and Carlos Mateos, Agere Systems; Andreas Lutz, KLA-Tencor

Session VI: Yield Modeling and Analysis II

Chairs: Patricia Gabella, International Sematech (AMD assignee); and Thomas Piliszczuk, KLA-Tencor

Invited Paper: Statistical Bin Analysis on Wafer Probe

Sebastián Muriel, Oscar Maire-Richard, Francisco García, Miguel Recio, and Carlos Cano, Agere Systems

Benchmark Comparisons for Yield Optimization in the Mature Fab

Melvyn Effron, HPL

Wafer-Level Stress Data Successfully Used as Early Burn-In Predictor

Miguel A. Merino, Agere Systems

Review Sample Shaping Through the Simultaneous Use of Multiple Classification Technologies in Impact ADC

Phil Wootton, Motorola

Session VII: Defect Detection and Reduction (sponsored by Applied Materials)

Chairs: Dave Gross, AMD; Walter Schoenleber, Applied Materials; Volker Tegeder, Infineon Technologies

Invited Paper: Efficient Killer-Particle Control Using Reliable High-Throughput
SEM-ADC

Kenji Watanabe, Yuji Takagi, Kenji Obara, Hirohito Okuda, Ryo Nakagaki, and
Toshiei Kurosaki, Hitachi

Design and Application of Gray Field Technology for Defect Inspection Systems

Silviu Rheinhorn, Danny Some, Ido Hammer, and Paul J. Wright, Applied Materials

An Investigation of Circular Resist Residue Defects in the Development of a 0.16-µm Flash Process

Jeff Erhardt, Koi Phan, and Jerry Cheng, AMD

Using a Pattern Monitor Wafer on an Inspection Tool for Chamber Recoveries

Dan Audette and Mike Triplett, IBM Microelectronics

9:00 a.m.–5:00 p.m.

Front-End Technology Conference

Session I: Front-End Technology Issues Confronting the Material Suppliers

Chair: James Moreland, Wacker Siltronic

Silicon Material Quality for Deep Submicron Design Rules

Wilfried V. Ammon, Wacker Siltronic

Advanced CMOS/SOI: Technology and Design

Jean-Luc Pelloie, LETI/CEA-Grenoble

Silicon Germanium Technology

Dr. Tillack, IHP Microelectronics

Electronics Specialty Gases: Status and Future

Jean M. Friedt, Air Liquide

Recent Advances in Wafer Cleaning

Paul Mertens, IMEC

Session II: Materials Issues for 100-nm and Below Technology Nodes

Chair: Daniel Bensahel, STMicroelectronics

Gate Stack/Shallow Junction Challenge for sub-100-nm Technology Generations

Howard R. Huff, Georges A. Brown, and Lawrence A. Larson, International Sematech

ALCVD Technique

Speaker TBA

Shallow Junctions for Advanced Silicon Technology

Peter Stolk, Philips Research

Advanced Cleaning Technology for Front-End Applications

Stephan de Gendt, IMEC

High-Speed Si/SiGe Heterostructure Device Technology

Steven J. Koester, IBM

9:00 a.m.–5:30 p.m.

Wafer-Level Packaging Conference (in cooperation with SECAP, Semiconductor Equipment Consortium for Advanced Packaging)

Chair: Eric Beyne, IMEC

Keynote Address

Phil Garrou, Dow Chemical

Market Trends in the Advanced Packaging Industry

Neil Moskowitz, Prismark Partners

Wafer-Level CSP and Bumping for High-Density Flip Chip

Michael Töpper, Fraunhofer Institute for Reliability and Microintegration

Sputter Technology and Equipment for Under Bump Metallization

Hans Auer, Unaxis

Photolithography Systems for Advanced Packaging

Dietrich Tönnies, Karl Suss

Wafer-Level CSP for System in Package

Junichi Kasai, Fujitsu

Large-Area Precision Photomasks for Advanced Packaging Applications

Jim Quinn, Image Technology

High-Aspect-Ratio Photoresists for Wafer-Level Packaging and Wafer Bumping

Elmar Cullmann, Karl Suss

Low-Cost Production of Thin-Film Multilayer Silicon Substrates for High-Density Interconnect and Multichip Packaging

Hans-Wolfgang Diesing, Strand Interconnect

Electroplating Technology for Wafer Bumping and Wafer-Level Packaging

Paul Siblerud, Semitool

3-D Lithography in Wafer-Level Packaging

Tami Mazel, Shellcase

A Roadmap to Gold Bump Design Rules for LCD Drivers

Jörg Jasper, EM Microelectronic-Marin

Panel Session: "Challenges and Opportunities for Low-Cost CSP Technologies"

Chair: Ron Leckie, Infrastructure

WEDNESDAY, APRIL 25

8:30–10:45 a.m.

Semiconductor Equipment and Materials Market Briefing

Speakers: Elizabeth Schumann, Director, Industry Research and Statistics, SEMI; and Dan Tracy, Senior Market Analyst, SEMI

9:00 a.m.–5:00 p.m.

Interconnect Technologies Conference

Session I: Interconnects

Chair: Dirk Graavensteijn, Philips Research

Title TBA

Karen Maex, IMEC

Copper Plating for the Formation of Interconnects

Andreas Thies, Atotech

Effect of Interconnect on Performance of ICs

Harry Veendrick, Philips

Session II: Dielectrics

Chair: Günter Schmid, Infineon Technologies

Title TBA

Jeffrey C. Hedrick, IBM

Addressing a Novel Oxazole Polymer for Ultra Low-k Dielectrics

Takashi Enoki, Sumitomo Bakelite

Title TBA

Gill Yong Lee, Infineon

Cleaning Challenges of Dual Damascene (Low-k/Cu) Integration

Didier Louis, LETI CEA

Thermal Simulation of ULSI Interconnection Systems and MEMS

Reinhard Streiter, Chemnitz University of Technology

STEP: SEMI E79, Measuring and Managing Equipment Performance Using SEMI
International Standards

Chair: Jim Irwin, I/C Irwin Consulting

Introduction to SEMI Standards for Equipment Performance Measurement

Jim Irwin, I/C Irwin Consulting

Overview of SEMI E10 Content and Usage

Sal Diiorio, Brooks Automation

Overview of SEMI E79 Content and Usage

Tom Pomorski, Fairchild Semiconductor

Managing OEE at STMicroelectronics

Thomas Vonderstrass, IPC; and Peter Gaboury, STMicroelectronics

The German Government Project on Improved Equipment Efficiency

Josef Bichlmeier, CamLine; and Andreas Rudolph

Q&A on Standards and How/Why to Use Them

12:30–5:30 p.m.

Fifth Fab Management Forum

Chair: Joël Monnier, STMicroelectronics

Market Briefing Highlights

Elizabeth Schumann, Director, Industry Research and Statistics, SEMI

Session I: Best in Class Technology and Development Cycles

Session II: Advanced Manufacturing Process and Tool Control

Session III: Yield Management and Defect Control

1:00–1:30 p.m.

SEMI International Standards Program Overview

Exhibitor Forum Hall B3

1:00–5:00 p.m.

Environment, Health, and Safety: Preparation for EHS Incident Management and Recovery in a Modern Wafer Fab

Chair: Alastair Brown, Rushbrook Consultants

Preliminary Agenda

Basics of a Successful Incident Recovery

Bob Barnes, Robert Barnes Associates

Insurance Program and Risk Management Issues

Graham McGee, Regional Manager, Marsh Risk Consulting

Organizing and Structuring a Global Business Continuity Program

Greg Valentine, Global Risk Manager, Applied Materials

A Case Study of a Disaster

Peter Middleton, EH&S Adviser, Filtronic Compound Semiconductors

2:00–5:00 p.m.

Workshop: Analytical Methods for Process Chemicals

Chair: Klaus Klemm, Merck

Analytical Technology As a Support Tool for Optimized Total Chemical Management (TCM) Operation in S/C Fabs

Robert Preisser, Merck

Requirements of Chemical Qualities Used for Semiconductor Manufacturing at Infineon

Germar Schneider, Infineon Technologies

Chemical Analytical Methods for Monitoring of Metal Contamination in Semiconductor Manufacturing at Infineon

Oliver Luxenhofer, Infineon Technologies

Contamination Characterization in Daily Routine of Semiconductor Materials
Using ICP-MS

Peter Vullings, Philips

The Need of Sample Preparation for Trace Element Analysis and New Techniques to Get Rid of It

Klaus Klemm, Merck

Analysis of Anionic Trace Impurities in HF and NH₄F

Wilhelm Blödorn, Honeywell

Particle Measurements in Electronic-Grade Chemicals—Current Limits and Future Requirements

Stefan Kunz, Merck

Importance of Analysis for Gas Supply to the Semiconductor Industry

Jürgen Bierhals, Messer Griesheim

Specifications and Analytical Methods for Ultrapure Water

Rolf Nagel, Haager & Elsässer

Analytical Method Validation in the Semiconductor Industry Applied to High-Purity Hydrogen Peroxide

Jean-Marie Collard, Solvay Interox

THURSDAY, APRIL 26

9:00 a.m.–5:00 p.m.

STEP: Standards for 300-mm Manufacturing

Chair: Margaret Pratt, International Sematech

11:00 a.m.–1:00 p.m.

Workforce Development Forum

Exhibitor Forum Hall B3

1:00–5:00 p.m.

International Workshop on Lead- and Halide-Free Electronics

Chair: Ruben Bergman, Executive Director of HDP User Group International

FRIDAY, APRIL 27

10:30 a.m.–5:00 p.m.

Organic Airborne Molecular Contamination in Semiconductor Manufacturing— Scientific News and Effects

Fraunhofer Institute IIS-B, Schottkystrasse 10, Erlangen-Nürnberg, Germany

Chair: Dr. Lothar Pfitzner, Fraunhofer Institute of Integrated Circuits — Dept. B

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