Roadmap committee steers chipmakers onto faster route with ITRS update

Bowing to the rapid pace of process development, the international team writing the semiconductor industry's technology roadmap has issued an interim update of the document.

The mid-course correction to the 1999 International Technology Roadmap for Semiconductors (ITRS) revises the map's technology node timelines and pinpoints technologies such as metrology and defect reduction that require some improvements in several key areas. Most important, the writing committee lays out three scenarios for potential node trends as they apply to DRAM half-pitch for 2001. That year is the date for the next official revision.

A primary impetus for the update is the fact that chip production at the 130-nm technology node will begin this year and not in 2002 as forecast in the 1999 ITRS. The update notes that the International Roadmap Committee (IRC) pulled the 180-nm node in one year to 1999 just as members were putting the finishing touches on the 1999 ITRS in November. Amid great debate, the industry decided to stick with the original three-year intervals between technology advances in DRAM half-pitch chips in the 1999 document rather than move to an accelerated two-year cycle.

Yet, lo and behold, the industry finds itself at the 180- and 130-nm nodes nearly a year ahead of time, thanks mostly to chipmakers' ability to stretch lithographic capabilities. The three scenarios proposed in the update take note of this reality. The proposals roughly run from least to most aggressive. Scenario 1.0 pulls in the 130-nm DRAM half-pitch node to 2001 before intersecting with the original 1999 ITRS 100-nm target year of 2005. Scenario 1.5 pulls the 130-nm node into 2001 but moves the 100-nm node to 2004 from 2005. Scenario 2.0, the update's most aggressive proposal, pulls the 130-nm node to 2001 and "corrects" the original 100- , 70- , 50- , and 35-nm nodes, making them 90 nm, 65 nm, 33 nm, and 23 nm, respectively.

For the purposes of simplification, the IRC and the International Technology Working Groups (ITWGs) used the most aggressive of the three scenarios, Scenario 2.0, to develop the updated tables showing the overall roadmap technology characteristics, or ORTCs. This scenario pulls in the 100-nm node to a two-year timeline and proposes changing it to 90 nm. Even though the node has been called 100 since 1992, it's more of a philosophical question and a matter of nomenclature that doesn't necessarily reflect the actual progression, the committee believes.

Bob Doering, a senior fellow at TI and one of the two North American chairmen on the 10-member IRC, says that without question, "the overall trend is toward being a little more aggressive." Although not every ITWG is on board with the faster approach, the differences between the DRAM and microprocessor camps over whether to proceed at two-year or three-year intervals have narrowed, says Doering.

The working groups are spread among five regions globally. The infrastructure for Japan's regional ITWG is well developed, says the North American cochairman. "I think they have more people working on these issues domestically. Because of that, they have tended to take a more comprehensive engineering view. That's very valuable because it drills down into a lot of the details, and it doesn't require a lot of discussion.

"It's a natural outcome of that sort of thinking, when you devote that much effort to come up a little more on the conservative side," Doering continues. "When you're more in the top-down, shooting-from-the-hip mode, you tend to think more like 'let's just throw out the challenge.' I think some of the differences...are a natural reflection of how many man-hours are being spent, and it influences the philosophy."

Doering emphasizes the need "to strike a balance between a top-down, let's-go-for-it [approach] and some degree of counterbalancing with engineering analysis. We try to do that, and some regions contribute more in one way than another. But generally, those differences of approach and philosophy have decreased a lot in the past couple of years, partly because more of the regions have developed infrastructures, and that tends to push everyone a little more in that direction. Despite that, I'd say the roadmap acceleration is continuing simply because it is very obvious that the industry is in an extended period of moving very fast." The question, says Doering, is, "How much longer can we continue at two years before it slips back to three?"

What's driving the industry to put the pedal to the metal? "I'd say competition," Doering responds. "Of course, it had to be enabled by a whole lot of hard work and incremental improvement." Those improvements have come from some unexpected quarters, primarily in lithography. "It's getting shorter wavelengths that gives you the...most brute force in lithography." The willingness of people "to pull out all the stops, what some people call 'tricks,' to push all the other aspects of lithography."

The most obvious area is "very high numerical apertures, but even beyond the lithography tools one of the big changes in the last two years is the use of optical proximity correction. That's made a big difference, as well as continuing advances in photoresists."

Defect reduction and metrology technologies require some tricks of their own, as noted in the update. In metrology, critical dimension measurement capabilities need to meet precision requirements for CD control over the next five years. There are also depth-of-focus issues facing CD-SEM and a great challenge to meet precision needs, such as tool matching for high-k materials film-thickness measurement, as well as precision improvements for oxide gate dielectric film thickness.

The aggressive scenario under consideration can create problems "when technology nodes are accelerated beyond our historical defect reduction learning rates," points out David Jensen, cochairman of the roadmap's defect reduction ITWG. Jensen says Scenario 2.0 is "still within historical learning rates for defect reduction."

The most aggressive scenario represents a "logical" approach to technology node forecasts because it is "precisely a 50% reduction in half-pitch every six years," he adds. No real consideration was made for defect reduction during the discussions of the three scenarios, Jensen says. The focus fell primarily on chip size and lithographic capabilities.

Asked to identify any one specific area for improvement in defect technology, Jensen points to advanced process control in order "to improve systematic yield. The bottom line is that tool defectivity, although maybe not meeting all targets, is under control. We understand pretty well how to clean tools and keep them from showering hard defects onto wafers. However, it's process variation that is difficult to control from wafer to wafer and lot to lot. Advanced process control gives the ability to control these tool variables such as temperature, deposition time, pressure and the like and address the systematic yield component."

Jensen notes that the yield component offers "a much greater revenue lever than defectivity. Just look at the difference in price between a 1.2-GHz part and a ~900-MHz part."

The update is merely one of a series of snapshots or talking points along the road to consensus, Doering says. The goal is to finish the scenarios "that determine the overall roadmap characteristics." The next meeting is set for Europe in March. Following the European confab, the committee will finish an outline and determine the timing of the nodes before the separate technology working groups "put together a first pass at their chapters." Finally, everyone will meet at Semicon West 2001 in July in order to get feedback, or, as Doering puts it, "put up a straw man and get a broader audience" before preparing the next official revision.