Evaluating the yield impact of epitaxial defects on advanced IC technologies

Randy Williams and Robert Jacques, Intel; and Mustafa Akbulut and Wayne Chen, KLA-Tencor

A collaborative study that used an advanced unpatterned wafer inspection system found that epitaxial defects and their corresponding impact on device yield varied between wafer suppliers.

Silicon wafers with an epitaxially grown layer are widely used in the fabrication of advanced CMOS and bipolar transistor devices because the inherent properties of the film enhance the devices' electrical performance.^1,2 The epitaxial, or epi, layer typically possesses well-controlled dopant concentrations and can achieve a near-perfect crystalline structure. Fortunately, the layer is free from crystal- originated pits, which are common with nonepitaxial silicon wafers and can have a negative impact on gate oxide integrity.^3,4 However, the epitaxial process can generate a variety of epitaxial defects within the layer, including stacking faults, epi-spikes, mounds, hillocks, and pits, which cannot be removed by conventional semiconductor cleaning methodologies.^1,5 Depending on their type, size, and location, as well as on the device design and yield sensitivity, such epitaxial defects can adversely affect product yields.^6­8 As a consequence, it is critical to control or eliminate these defects by using tighter defect specifications for incoming wafers.

In the past, it has been difficult to assess the overall yield impact of epitaxial defects because the defect sensitivity and capture rate have been poor with existing product wafer inspection systems. Furthermore, the ability to classify these defects depends on the accuracy of defect classification and the defect review sampling methodology. To better understand and quantify such defects' yield impact on an advanced semiconductor manufacturing process, a joint project was initiated between an Intel fab in Rio Rancho, NM, and KLA-Tencor (San Jose). In this project's initial phase, incoming silicon wafers from three major wafer suppliers were inspected using KLA-Tencor's Surfscan SP1^TBI unpatterned wafer inspection system. A newly developed defect classification algorithm enabled the tool to perform real-time defect classification (RTDC) to assist in the evaluation of the yield impact of epitaxial defects.⁹

The propagation of the epitaxial defects during subsequent semiconductor processing was then closely monitored using the fab's existing in-line wafer inspection systems to evaluate the relative defect sensitivities and capture rates at selected product inspection locations. After processing was completed, the product die were tested electrically and bitmaps of the electrical failures were generated. By comparing the yield results provided by the bitmapping analysis with the incoming wafer inspection (SP1^TBI) results, the kill rates and yield impact of the epitaxial defects were accurately determined. Because the defect levels and the corresponding yield impact varied significantly between the three wafer suppliers, these results indicate the need for further refinement in the defect specifications for incoming wafer cleanliness.

Epitaxial Defects

Epitaxial defects often appear as three-dimensional defects (such as stacking faults, epi-spikes, mounds, hillocks, and pits). These defects can be attributed to mechanical stress, which can be induced by crystal imperfections at the interface between the silicon substrate and the epitaxial layer, by chemical contamination in the silicon substrate, or by irregular processing conditions within the epitaxial deposition reactor. Stacking faults, the most common of the epitaxial defects, typically appear as square features for a <100> silicon crystal orientation (which is often used in the fabrication of MOS devices), as shown in Figure 1a. The size of the stacking fault depends on the thickness of the epitaxial layer. In contrast, epi-spikes are irregularly shaped polycrystalline defects that can be as large as 100 µm. These defects typically appear on top of stacking faults, as shown in Figure 1b, and their size is independent of the epitaxial layer thickness. As seen in Figure 1c, a mound or hillock is a pyramid-shaped structure that occurs on the epitaxial surface. These defects are nucleated between the epitaxial layer and substrate interface as a result of various crystal imperfections, and their height is limited to several microns (to a maximum of 20% of the thickness of the epitaxial layer).⁹

Figure 1: The three most common three-dimensional epitaxial defects: (a) a stacking fault, (b) epi-spikes, and (c) a mound or hillock.

Defect Inspection System

The SP1^TBI unpatterned wafer inspection system achieves better defect sensitivity than other conventional systems that have been in widespread use and can detect defects as small as 60 nm on bare silicon wafers. In addition, this inspection system provides high capture rates for many types of defects because of the optical configuration it uses.

As shown in Figure 2, the optical configuration of the system includes a normal- and oblique-incidence laser beam, along with two azimuthally symmetric dark-field collection channels. The wider of these two channels (PMT1) collects scattered light for half-angles ranging from 25° to 70°, while the narrower channel (PMT2) collects scattered light for half-angles ranging from 5° to 20°. In general, the dark-field wide (DFW) channel provides better sensitivity for small defects, whereas the dark-field narrow (DFN) channel provides better sensitivity for most epitaxial defects, including stacking faults, epi-spikes, mounds, hillocks, and pits. Both detection channels are axisymmetric and can detect anisotropic light scattering from particles, epitaxial defects, and scratches with a high level of efficiency regardless of the defect shape or orientation on the surface of the wafer.³

Figure 2: Schematic showing the optical configuration of the unpatterned wafer inspection system under investigation in the study.

The system is capable of differentiating between particles and various types of epitaxial defects because of its use of both normal and oblique illumination in conjunction with multiple detection channels. The light-scattering response produced by particulate defects can often be differentiated from that produced by epitaxial defects based on the angular-resolved scattering intensity. A new defect classification algorithm enables the system to discriminate between particles and epitaxial defects in real time and is based on the ratio of the light intensities from the DFN and DFW channels. For a particle, the light-scattering response from these two dark-field channels is similar (DFN/DFW 1). In contrast, epitaxial defects are detected and sized differently by the two channels (DFN/DFW 1). Consequently, the ratio of the respective light intensities (DFN/DFW) serves as the primary basis for the real-time defect classification of particulate and epitaxial defects.

In addition to the two dark-field channels, the system collects light from the normal-incidence laser beam through a bright-field channel, which uses the Nomarski differential interference contrast technique.¹⁰ This channel is very sensitive in detecting shallow scratches, slip lines, dimples, large mounds and other large epitaxial defects that do not scatter light significantly. With oblique-incidence illumination, the beam has three light polarization states: parallel to the plane of incidence (P), perpendicular to the plane of incidence (S), and circular (C). These polarization states can have an impact on the defect sensitivity of the inspection system by influencing the amount of light that is scattered and by affecting the angular distribution of the scattered energy. The P-polarization state is widely used to capture small defects on well-polished silicon wafers, while S-polarization is often selected to detect defects on relatively rough surfaces.¹¹ C-polarization is used with many thin-film applications to minimize the effects on defect sensitivity of variations in film thickness and uniformity.

Incoming Wafer Inspection Results

A total of 200 200-mm epitaxial wafers produced by three major silicon wafer suppliers were fully characterized in this study. Before any semiconductor processing, the incoming wafers were inspected by the SP1^TBI system at normal incidence, with large dynamic ranges for both the DFW and DFN channels. The defect sensitivity was optimized to provide a very high signal-to-noise ratio (greater than 8:1) to ensure that the level of false counts was <1 ppm.

Almost all of the particulate defects that were detected on the incoming wafers were <0.4 µm in size (as indicated in Figure 3), demonstrating that conventional wafer-cleaning techniques are effective in removing particles >0.3 µm in size. While the measured sizes of these small particles provide an adequate sizing estimate (based on calibration using PSL spheres), subsequent microscopic examination revealed significant errors in the sizing of many of the epitaxial defects. For example, large stacking faults and epi-spikes were often measured as being considerably smaller than they actually were because of the relatively low levels of light that are scattered from these types of defects. However, most of the epitaxial defects could be readily distinguished from particulate contamination based on size, since most of these defects (92%) were >0.3 µm, as Figure 3 also shows.

Figure 3: Defect classification by size. (Defect sizes were determined with the PSL-sphere-equivalent technique.)

Using the new RTDC algorithm, all of the detected defects were then classified as either particles or epitaxial defects based on their respective light-intensity ratios (DFN/DFW), as shown in Figure 4. Those defects with light-intensity ratios between 0.8 and 1.2 (DFN/DFW 1) were classified as particles, while the remaining defects were classified as epitaxial.

Figure 4: Defect classification based on light-intensity ratios.

Subsequent review of the epitaxial defects with a confocal microscope revealed that the RTDC algorithm was very accurate in discriminating between particles and epitaxial defects (>99% accuracy). As part of the off-line review, the defects were further classified into five distinct classifications: stacking faults, epi-spikes, mounds or hillocks, pits, and particles. These classification results, summarized in Figure 5, indicate that epitaxial defects are the dominant detractors that affect incoming wafer cleanliness, accounting for nearly 75% of the defects that were detected by the SP1^TBI system.

Figure 5: Types of defects identified on incoming wafers.

For purposes of comparison, the incoming wafers were also examined with the fab's existing unpatterned wafer inspection system, a Surfscan 6XXX from KLA-Tencor. As seen in Figure 6, that system's capture rates for particles and epitaxial defects were 97 and 92%, respectively. As expected, the SP1^TBI system provided better defect sensitivity and capture rates for both types of defects.

Figure 6: Defect capture rates of various inspection systems at selected points before and during semiconductor processing.

Process Monitoring Results

The impact of epitaxial defects during semiconductor processing was closely monitored to evaluate the relative defect capture rates for the AIT-X and KLA 213X product inspection systems used at selected locations within the process flow. The defect sensitivity and capture rates for these systems is typically not as good as that obtained on the incoming wafers with unpatterned wafer inspection systems. Moreover, as shown in Figure 6, the capture rates for both particles and epitaxial defects decreased as the wafers underwent further processing, regardless of the inspection tool used. The decrease in particle capture rates is to be expected, since incoming particulate contamination is usually removed during cleaning and etching operations or is covered up by thin-film depositions. However, epitaxial defects cannot be removed by conventional cleaning methodologies, and the impact is often evident during subsequent processing steps.

Because most epitaxial defects are relatively large, they often cause patterning damage during semiconductor processing, which leads to product yield losses. Figure 7 shows examples of epitaxial defects—a mound and stacking faults—that were detected at two different inspection steps using the KLA 213X inspection system. These defects ultimately resulted in a product yield failure (an electrical short).

Figure 7: Examples of epitaxial defects detected during semiconductor processing include a mound and two stacking faults.

Despite the relatively poor capture rates obtained with the product wafer inspection systems, the semiconductor patterning damage that occurred during processing enabled the in-line product inspection systems to detect some epitaxial defects that were not detected on the incoming wafers. The capture rates for the SP1^TBI inspection system depend on the defect type. As shown in Figure 8, the system's capture rate for particles was nearly 100%, whereas its capture rate for epitaxial defects was 74 to 83%.

Figure 8: Capture rates of the unpatterned wafer inspection system by defect type when its results were compared to those for product wafer inspection systems.

Yield Impact Assessment

Historical results from in-line inspection of product wafers indicate that epitaxial defects can have a negative impact on product yields, depending on the respective semiconductor product designs and yield sensitivities. Because most epitaxial defects are relatively large, they are typically killer defects. However, the overall yield impact of epitaxial defects has been difficult to assess because product wafer inspection systems have relatively poor capture rates for these defects. Classifying these defects depends on the defect review sampling frequency and logistics, as well as the accuracy and repeatability of the defect classification. Consequently, it has been difficult to accurately assess wafer-to-wafer, lot-to-lot, and supplier-to-supplier differences in epitaxial defect levels and the associated yield impact.

In this study, the product die were tested electrically after the completion of semiconductor processing and wafer bitmaps of the electrical failures were generated. By comparing the yield results provided by the bitmapping analysis with the defect inspection results provided by the SP1^TBI system, it was possible to accurately determine the product yield impact of the epitaxial defects. The corresponding product yield loss ranged as high as six product die per wafer, which would result in millions of dollars in lost revenue per year for high-volume semiconductor manufacturers. As shown in Figure 9, the epitaxial defect levels and the corresponding product yield losses varied significantly between the three silicon wafer suppliers that were evaluated in the study. The product yield loss for the worst supplier was approximately 2.4 times greater than that for the best supplier. These results can be useful in the development of new defect inspection methods and tighter defect specifications for epitaxial wafers to minimize future yield loss.

Figure 9: Comparison of epitaxial defects and associated yield losses for wafers from three different suppliers.

Conclusion

In a collaborative study between Intel and KLA-Tencor, the SP1^TBI wafer inspection system was used to inspect epitaxial wafers for an advanced semiconductor manufacturing process. The results demonstrate that the system's enhanced defect sensitivity and better capture rates provide a significant improvement over other systems in the ability to detect epitaxial defects. With an advanced defect classification algorithm, it was possible to differentiate between particles and epitaxial defects in real time with >99% accuracy, as confirmed by off-line defect review using a confocal microscope.

The propagation of the detected epitaxial defects through the semiconductor process flow was closely monitored to evaluate the relative defect capture rates at selected product inspection locations. A yield impact assessment was then conducted using electrical testing and failure bitmapping. It was observed that the epitaxial defect levels on the wafers from different suppliers and the corresponding product yield impact varied widely. Consequently, these results can have a significant impact on the development of future defect inspection methodologies and defect specifications to control epitaxial defects for advanced IC technologies.

Acknowledgments

This article is based on a presentation given at the IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop held in Boston from September 12­14, 2000. Used with permission. The authors would like to acknowledge the project support provided by Mark Armstrong, Alonso Arreola, Kristin Brozovich, Debra Fenner, Cyril Hudson, David Miller, Tom Tong, and Bronwyn Wickes of Intel, and the constructive comments and project support received from Hubert Altendorfer, David Fletcher, Dale Guidoux, and Kurt Haller of KLA-Tencor.

References

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Randy Williams is the defect metrology manager at Intel in Rio Rancho, NM, where he is responsible for defect metrology, yield enhancement, and yield modeling activities. He is the chairman of the corporate defect metrology engineering teams, which comprise 10 advanced semiconductor facilities. Williams has more than 17 years of experience in defect metrology and yield enhancement. Before joining Intel in 1996, he worked as a defect reduction project manager at Sematech and as a lead engineer and team leader at IBM. He has published numerous papers and technical reports, holds a patent in the field of defect metrology, and is a member of ASMC's technical committee. (Williams can be reached at 505/893-6929 or randy.r.fab11.williams@intel.com.)

Robert Jacques is an electrical engineering student at Clarkson University (Potsdam, NY) who supported several engineering projects from January to August 2000 in the defect metrology group at Intel in Rio Rancho, NM. He was awarded a Clarkson Merit Scholarship and is a member of the Institute of Electrical and Electronics Engineers.

Mustafa Akbulut is a staff research scientist in the wafer inspection division of KLA-Tencor (San Jose). Since joining the company in 1997, he has been involved in activities related to real-time defect classification and system characterization. Previously, he worked at Surface Science Laboratories (SSL) in Mountain View, CA, as a senior surface analysis engineer. Before joining SSL, he worked as a postdoctoral fellow at Rutgers University (Piscataway, NJ). Akbulut has authored and coauthored more than 20 publications on wafer inspection applications for yield control and in the area of surface science. He received an MS in physics from Rutgers University and a PhD in surface physics from Stevens Institute of Technology in Hoboken, NJ. (Akbulut can be reached at 408/875-7176 or mustafa.akbulut@kla-tencor.com.)

Wayne Chen is a senior technical manager for defect detection and process monitoring at KLA-Tencor. He joined the company in 1997 and has worked as an applications engineer, applications development manager, and senior applications engineering manager for defect detection, classification, and analysis. Previously, Chen was a staff scientist in device development at Raychem and a senior engineer at the Orton Ceramic Foundation. He received a PhD in materials science and engineering from the University of Notre Dame in South Bend, IN. (Chen can be reached at 408/875-7197 or wayne.chen@kla-tencor.com.)

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