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ROUND THE CIRCUIT

Start-up claims copper gains

A California start-up claims it has solved two major problems associated with submicron copper processes. ACM Research of Fremont, CA, has introduced two prototype tools based on processes developed at the company. One of the systems, the Ultra ECP, is capable of depositing copper interconnects on devices with geometries 0.035 µm. The other, called the Ultra SFP, can polish copper-integrated dielectrics with a k-value of 1.5. The two tools are ACM's first products.

The Ultra ECP uses an electroplating technique that puts down seed layers measuring 50 to 500 Å. Tests performed on customers' patterned wafers at its Class 10 lab confirm that the plating technology will meet the metallization requirements of the industry through 2010, according to ACM. Uniformity is <1% @ 1 x wafer-to-wafer and within the wafer.

The company developed its stress-free postdeposition polishing method to cope with soft low-k dielectric materials. The method, which eliminates the use of abrasive pads and CMP slurries, is the basis for the stress-free polishing (SFP) tool. The SFP system accommodates dielectrics with k-values of 3 to 1.8. The tool incorporates three polishing chambers and three cleaning chambers, which includes bevel and backside cleaning capability. The removal rate of 0.1 to 0.5 µm/min permits a throughput of 60 wafers per hour for 1-µm films, the company says. The elimination of consumables and 90% uptime mean users spend less than $2 per wafer, according to the vendor.

David Wang, cofounder and CEO of ACM, says his company invested 80,000 engineering man-hours in research and development of the systems since the company was formed in January 1998. Both tools accommodate 200- and 300-mm wafers.

Trio making 0.13-µm chips

Ten months after announcing their joint effort, three chipmakers have begun making 0.13-µm chips with advanced foundry technology. IBM in the United States, Infineon in Europe, and UMC in Taiwan are in the initial stages of manufacturing logic and mixed-signal chips. Initial shipments of high-performance chips for network communications and computing are scheduled for early 2001. The partners developed the processes at the IBM Semiconductor Research and Development Center in East Fishkill, NY.

The baseline technology combines low-k dielectric insulation and a high number of copper interconnect wires to give all three manufacturers the capability to make low-power, high-speed, mixed-signal, and RF devices. The three chipmakers are using multiproject test wafers and other means to expedite delivery of products to customers. UMC's Silicon Shuttle program allows customers to split the costs of photomasks, for example. The Taiwan-based foundry has more than 16 customers that are poised to start production of chips with the technology through the first quarter of 2001, says Fu Tai Liou, senior vice president and CTO of UMC.

$5B cleanroom market seen

A market research firm predicts the global market for cleanrooms will grow to $5 billion by 2005. In its World Cleanroom Markets 2000­2005 report, McIlvaine, of Northbrook, IL, says that demand from the semiconductor industry will spur the growth spurt. The chip industry accounted for cleanroom sales of $700 million in 1999. That figure is expected to reach $1.1 billion in 2000, according to McIlvaine. Sales to the disk-drive, FPD, pharmaceutical, and food industries account for most of the remainder of the total.

Although the majority of the customers are in the United States, the report notes that the cleanroom market is more dispersed than it has been in the past. Taiwan spent more for semiconductor cleanroom hardware in 1999 than Japan, according to the report. Malaysia is the world's biggest customer for disk-drive cleanrooms. The market for minienvironments is growing at a 25% annual clip, the report adds. Information: rmcilvaine@mail.mcilvainecompany.com.

Chipmaking book covers all

The new Handbook of Semiconductor Manufacturing Technology covers the technological and economic aspects of chipmaking in 37 chapters. The 1157-page reference work addresses the range of processes required to manufacture advanced devices. These include surface preparation, ion implantation, plasma etching, process control, in-line metrology, and yield management. Other chapters address topics such as factory modeling, the economics of semiconductor manufacturing, ESH, electron-beam lithography, and equipment reliability. The book's four appendices cover physical constants, unit conversion, commonly used standards, and acronyms. Contributing authors have experience in the device side, equipment side, academia, and consortia.

The editors are Yoshio Nishi, a senior vice president of TI, and Robert Doering, a senior fellow at TI. The foreword was written by TI's Jack Kilby, the coinventor of the integrated circuit and corecipient of the 2000 Nobel Prize in Physics. The publisher is Marcel Dekker. Information: http://www.dekker.com.

(A news feature on TI's Jack Kilby at the Nobel Prize awards ceremony in Stockholm, Sweden, and his lecture comments can be found on page 26 of this issue.)

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