Lassoing the future

In New York the state government has pledged $28 million toward construction of a $275-million 12-in. pilot fab in the Center for Advanced Thin Film Technology at SUNY/ Albany. In Maryland NIST is building what the institute calls "one of the most technologically advanced buildings in the world" in the Advanced Measurement Laboratory. IMEC, the university-based research consortium in Belgium, recently named nine major chipmakers as the first members of its new 157-nm lithography program. At the University of Rochester researchers have created quantum silicon dots that they claim will pave the way for atom-size transistors. On the other side of the country researchers using the same technology at the University of Southern California are "trying to build a computer that's beyond Moore's Law." MICRO's R&D Roundup gives readers a glimpse of the vast range of university and governmental research being conducted around the world. Issues touched on in this special year-end section include interconnect, environmentally friendly processes, low-k, copper, the role of partnerships, and the status of mentors and students in carrying on the work that will take the industry into the future. —John Conroy

	Kenneth Rose
	Professor of Electrical, Computer and Systems Engineering
	Rensselaer Polytechnic Institute
	Troy, NY

As a member of the Center for Advanced Interconnect Science and Technology, Rose is part of a research team that has developed RIPE, the Rensselaer Interconnect Performance Estimator. Available on-line, the software program models the characteristics of microprocessors with performance-related problems caused by the increasing number of interconnect levels. RIPE ties clock frequency, power, and other performance factors to interconnect cross sections and the number of interconnect levels.

"As you go deeper and deeper into submicron technologies you're going to find an explosion, really, in the number of interconnect levels required to meet [chip] performance goals, Rose points out. The large cross section wires "keep the resistance down to meet performance targets. Now think about making trade-offs between how many cross section wires you put on versus how many really big cross-section wires you put on. The smaller the cross section the larger the yield hit. Yield is going to be lower if you have a small cross section. That's inevitable."

Implications for BEOL Manufacturing Moving to deeper submicron technnology will require Smaller interconnect cross sections at the lowest levels. Cu/low-k interconnect materials. Longer wires with larger cross sections to meet wire resistance targets. More layers--more work. Smaller cross sections--more difficult work. Fortunately, small interconnect cross sections will not need to be combined with low-k dielectrics to meet performance goals.

Rose is also a codirector of the RPI Research Site for the NSF Industry/ University Cooperative Research Center for Microcontamination Control (CMC), which also has an R&D site at the University of Arizona. The center focuses on defect analysis to improve BEOL yield and strategies to enhance yields. The center is also tackling the interconnect problem, Rose says. "One of the ideas is to reduce the problem with interconnects by using 3-D technology," putting two wafers on top of one another. Running the long wires vertically rather than horizontally means they can be a lot shorter, Rose notes. But, he adds, "again, there are manufacturing issues." These involve, among other things, properly aligning the substrates. "It's tricky." Rose and colleagues were looking to make a proposal to an industrial advisory board this fall.

The CMC is also examining the effect of CMP slurries on wafer processing. "We have found that some slurry systems produce a lot of scratching and some don't." RPI is upgrading its microfabrication cleanroom to "8-in. capability," Rose says. "That's a little scary for a university."

	Vicky Diadiuk
	Assistant Director, Operations
	Microsystems Technology Laboratories, School of Engineering MIT
	Cambridge, MA

Semiconductor R&D shares the spotlight with several other disciplines at MIT's microsystems technology laboratories (MTL), says Diadiuk during a tour of the on-campus facility. "Overall, about 30% of the processes are for MEMS, 30% may be VLSI, and the rest are an oddball mix--biology, physics, some materials science, a little bit of mechanical engineering and chemical engineering."

The MTL facility includes three research labs. The integrated circuits lab is "the most industrial" of the three, while another lab on the building's fourth floor "is a more typical university lab with manual processors and so forth. The fifth-floor lab has a very dirtball-like cleanroom where any processes can go. As you get higher in the building you get dirtier and dirtier and more flexible. We like it that way, because we basically can accommodate people from any walk of life who want to do microfabrication."

For both practical and financial reasons, Diadiuk and her colleagues have high aspirations for the MTL. "Our mission is to be the premier microfabrication facility on campus, maybe the only one if we can get away with it. It's a very expensive building to run, and to therefore duplicate it throughout campus doesn't make sense. The IC lab is actually doing much more than ICs now, because anything that is CMOS compatible can go there." Approximately 50% of the CMOS processing involves MEMS that are compatible with the complementary metal oxide chip technology but do not require "the kind of fine lithography that some of the current CMOS devices do."

Private industry has provided cash support and equipment donations, Diadiuk says. She shows off a room "essentially built to accommodate two tools that Applied Materials gave us. One is an Endura physical vapor deposition system; the other one is an etcher." Lacking a subfab, the researchers had to be "very creative with installations." They set up the entire room for pumps, power supplies, chillers, and other peripheral equipment. "As you can see, the lines are kind of squirrelly on the floor, because we don't have a subfab. We're all in the same place, and that makes it kind of awkward to install. But we got them in here, and they're working like a charm."

The MTL is in the midst of converting from 4- to 6-in. processes, giving the facility a slightly disheveled appearance. "You'll see a lot of construction as we go through the lab. . .and the reason we want to go with the 6 in. is not so much that we want the wafer real estate as it is we want to have the new processes. We want to convert for three reasons: to get the new processes; to be compatible with Lincoln Labs and Analog Devices, which have fabs nearby with which we can exchange wafers and be a backup for each other; and to have newer machines because our old ones . . . are dying and it's hard to get parts for them."

MIT recently finished installing a copper CMP room housing a Strasbaugh Harmony 6 EG polisher among other tools. The goal is to offer 3-D interconnect, copper damascene, and related processes. The facility has "acquired really huge capabilities for wafer bonding and alignment as well as deep reactive ion etch. We are now able to etch through the wafer with almost essentially vertical walls."

A self-described "MIT lifer," the assistant operations director has worked at the MTL for five years since receiving bachelor and doctoral degrees in physics from the university. Diadiuk conducted research in compound optoelectronics at MIT's Lincoln Labs before coming to the MTL. "We have full cross-pollination. The guy who's running the group at Lincoln Lab came from MTL. We understand really well what our operations are like, and we do a lot of exchanging of wafers, processes, and students."

	Robert Hebner
	Director Center for Electromechanics
	University of Texas
	Austin, TX

Before taking his post at the University of Texas, Hebner says he was "very active in the semiconductor side" at NIST. During his tenure there, he spent 15 months working with DARPA in the lithography area. "When I was at NIST I talked a lot about why it was important for the U.S. economy that industry, university, and governmental partners really work together. The University of Texas called my bluff and said, 'Okay, we're doing to do it. Let's see you make it work.'"

Hebner now is involved in "novel ways of producing electric power and energy" using advanced semiconductor technology "to do things that people have never been able to do before. We're hoping to replace batteries on the international space station with small generators to save the taxpayer, according to NASA estimates, a little over $300 million. We couldn't have done it five years ago. We didn't have the materials and the semiconductors."

His new position gives Hebner a greater appreciation of the importance of cooperation. "I think partnerships are absolutely essential for the U.S. economy when companies today are under tremendous pressure to decrease the time to market of new technology. Therefore, they don't have the time to develop the next generation, the one after that, and the one after that. At universities we have the opportunities to be a little more forward looking."

One surprise did await Hebner following the transition from the halls of government to the groves of academe. Intellectual property agreements "are even harder [to devise] than I thought. Large companies have figured out how they will do these agreements, and they basically can't afford much flexibility. Small companies that don't do IP agreements . . . tend to be very concerned almost to the level of paralysis. A big concern for the U.S. economy broadly is how do we get new technology into companies that aren't used to taking new technology in?"

Small firms often "don't have a process for doing this routinely," Hebner points out. That's generally not a problem for chipmakers, though. "Most of the semiconductor people have to do this. If they're not on the cutting edge, they don't exist any more."

Universities can struggle trying to create comfortable partnerships with industry, according to Hebner. The difficulty stems from distrust and lack of expertise. "You get companies who are afraid that a university will steal ideas. The semiconductor industry has gotten around licensing more than a lot of other industries . . . because the industry knows it can't win by building a fort and standing still."

A quiet trend away from academic isolation is under way, although "university people aren't acknowledging that much of the really important work is collaborative," says Hebner. The people with whom you have to work aren't people down the hall; they're people in other places around the world." Opportunities to strengthen the quality of research "tend to break down the walls. We still have a very rigid and hallowed departmental structure," he adds, "but fundamentally the communication is working in such a way to permit that hallowed structure to not be in the way."

	Farhang Shadman
	Director
	NSF/SRC Research Center for Environmentally Benign Semiconductor Manufacturing, University of Arizona
	Tucson, AZ

After four years and more than 35 projects the ERC has raised the profile of environmental, safety, and health issues (ESH) and showed the wisdom of thinking green in the semiconductor industry, maintains Shadman. "Various projects at the center have now demonstrated that environmental gain means reducing waste, increasing efficiency, improving process integration, and developing innovative methods of process and factory optimization."

The ERC has made breakthroughs in several areas says center's director. One key advance is in water purification. "We are working on a new generation of processes that have two characteristics. First, they combine various purification steps such as oxidation, filtration, and degasification in one integrated process. They do the same with integrated CMP waste processing, water recovery, and metal recycling in CMP and post-CMP cleaning. Second, these are low-energy techniques, so we do not end up spending more energy and using more chemicals as a result of reducing water usage or recycling."

Shadman points out that many conventional water-recycling processes use so much energy and chemicals that they "do not represent a true environmental gain." He adds that in the next five years the ERC needs to focus more attention on energy usage by fabs and process tools. Novel environmentally benign planarization and issues related to new materials are two other areas the center will pursue.

ERC researchers have reached their stated goal of developing new photoresists "developable in supercritical carbon dioxide," notes Shadman. A joint effort among MIT, Cornell, and Arizona State has resulted in the development of "a sequence of processes for environmentally benign deposition and patterning of low-k materials that are photo-imageable. This sequence will eliminate the need for photoresist and organic solvents. It also reduces the process steps by a factor of two."

Shadman foresees a gradual move to more collaboration between ESH experts and process experts. "Other trends will include moving away from organic solvents and aggressive chemicals, a significant reduction in the use of PFCs, the development of new fabrication methods that will minimize the use of CMP as we know it, and process integration that will reduce successive cleaning and recleaning."

Even though most chipmakers recognize the importance of considering ESH in manufacturing, Shadman believes the industry needs to travel a bit farther before it begins to integrate green concepts in the design of tools and processes. "We still have a long way to go to implement design for environment. There's this prevailing myth that environmental gain means compromise in performance and increase in cost. We need to change this false premise by presenting facts and solid proof."

During its infancy the semiconductor industry had less reason to worry about the environmental impact of its manufacturing processes, Shadman says. Those relatively carefree days are gone. "Because of the unprecedented growth of the semiconductor industry, tremendous dependence on various resources, the number of new chemicals, and the widespread use of products by consumers, the environmental impact is no longer small. In fact, it can become a major obstacle to sustainable growth."

In addition to the University of Arizona, the center involves the efforts of five other universities and one research laboratory: Arizona State, UC Berkeley, Stanford, Cornell, and MIT, and Lincoln Labs. Seventy-three graduate students have participated in center research, and more than 80 undergraduate students "have received some research experience." The ERC has established an outreach program designed to attract high school students to careers in science and math. The program also backs training for high school science teachers.

"The companies that have joined the ERC are those that have long-term vision and commitment to novel science and technology ideas, and therefore like to see this strategic approach by the ERC." The approach is to examine fundamental environmentally benign methods, "which have timeless relevance and importance," he says.

The U.S. semiconductor industry leads the rest of the world in developing novel processes, Shadman asserts. Other countries have placed greater emphasis on life cycle studies. "ESH is more global than most other aspects of manufacturing; as such, it calls for global collaboration. The ERC is going beyond U.S. boundaries and currently has an international membership and does collaborative research with several leading universities and research organizations in other countries."

"Rapid fault isolation is one of the really serious challenges" in submicron chip manufacturing, asserts Dellin, a former deputy director for reliability in the Sandia failure analysis group. For a decade he and his colleagues have worked on methods "to rapidly isolate faults on ICs."

A faulty microprocessor or ASIC has "tens of millions" of possible defect locations. Finding them is a challenge that has become increasingly difficult, Dellin notes. "The basic analogy I use is that finding defects on chips is like finding a needle in a haystack where every two years the haystack gets bigger and the needle gets smaller," he says. Using "brute force" SEMs is time-consuming, Dellin points out. The techniques he and fellow researchers developed "basically make the defect light up." The methods involve applying "stimulation to just part of the circuit" in order to produce a localized disturbance.

"The basic idea is to raster this stimulus across the integrated circuit and measure the voltage required to supply a constant current to the device and then make a false color image," Dellin explains. Most of the IC will be one color, except where there's a change in the voltage required to supply the chip with constant current near various types of defects. The techniques are effective for finding opens, shorts, ruptured oxide, and other faults. These approaches are "orders of magnitude faster than trying to do brute-force raster and high-magnification SEM analysis" for the seemingly infinite number of fault sites, Dellin notes. "All you need is to find the one; that's what we do."

Sandia applies some internal funds to the research efforts. The project also receives some support from IC manufacturers. The efforts have paid off. "We've been awarded at least 10 patents in the last decade," Dellin says.

Affiliated with 63 North American universities, SRC has decided it needs to tap into a deeper talent pool. "We'll be going global next year," says Cavin. "All of our member companies are global. They do business around the world . . . and a major reason [for this decision] is we need to be where they are. They're facing some challenging technological problems. We need to get the best minds to work on them." SRC has a research budget of nearly $30 million and more than 800 graduate students working in its programs, Cavin says.

Those best minds will be put to work in "the whole range of areas that relate to front-end process technology" in four science areas SRC covers. A simple example of the organization's focus is its investigation of alternatives to gate oxides. "As transistors shrink, the gate oxide is thinner and thinner and therefore more leaky. . . . Mainly, we're trying to extend the life of the bulk planar CMOS device. We have some very excellent programs in those areas, and I'm pretty optimistic [about the near future]."

Looking beyond bulk planar CMOS to dual-gate types of structures the picture gets slightly overcast, but Cavin remains sunny that the research community will be up to the task. "I'm optimistic that we will be able to extend this technology for at least another decade through a variety of inventions and changes. It's not going to be easy; I'm not minimizing the [difficulties]. The interconnect area is a challenge, because copper and low-k are pretty difficult to understand."

Cavin believes SRC will contribute to developments for "that whole area on interconnect technologies beyond copper and low-k." The advent of communications chips has had an impact on the area of mixed signal design. RF signals captured and processed by these chips is a "whole regime" that will drive technologies, particularly low-voltage analog devices. "My opinion is that there will be technological innovations to satisfy those needs," Cavin asserts. "I hope I'm right."

	Ahmed Busnaina
	William Lincoln Smith Professor Mechanical Engineering Northeastern University
	Boston, MA

The ITRS guidelines project that trench aspect ratios are heading further down into the submicron regime, to 50 nm or lower, notes Busnaina, who recently took the professorship at Northeastern. Chipmakers working with wet processes still need to rinse and clean wafers. "When you get to that depth it's very hard to get liquid in there, and, more important, hard to get it out of there," he emphasizes. What to do?

Continuing work begun at Clarkson University in Potsdam, NY, Busnaina and a research colleague are using modeling to explore "using megasonic pressure waves and acoustic pressures to put fluid in and push it out. They have a positive and negative pressure." Two parameters are involved--frequency and intensity, Busnaina points out. "Frequency would be a function of size. The smaller the size of the wave, the higher the frequency." For a submicron trench "you have to be in the megahertz range. As for amplitude you need to have enough pressure force to overcome the capillary force. You can control that by the megasonic intensity. We've been doing a lot of modeling on that" in order to gain insight into how the method works.

The two researchers presented the pressure technology at an interconnect conference at International Sematech, and they've talked with private companies about funding. "We had a lot of positive feedback from people who thought this was a good thing," Busnaina says. Encouraged by the response, the pair have sent a proposal to the National Science Foundation.

They've received some material and technological support in the form of metrology from Sematech and other companies, Busnaina says. He is continuing to work with students at Clarkson through the 2000­2001 academic year. "We're also using the same technology to do copper electroplating," he points out. The Clarkson research team faces similar problems. "You want to have the fresh chemicals in and out. You would do plating from the bottom of the trench. You also want to overcome using additives." He says that by using megasonics "we don't get voids, because we don't use additives."

Convection "will take the chemistry inside and outside. You go in and plate. If the chemical is consumed, you push in the fresh chemicals. It's like a mini-pump at each trench that's replenishing the solution in each trench constantly. And we do get bottom-up fill," Busnaina explains. The results confirm the cleaning aspect, although it is difficult to clean ionic contamination from the bottom of a trench, he notes.

The NSF proposal is designed to verify that the method works. "It does work with electroplating. We've plated 0.3- and 0.18-µm trenches. Those are just the preliminary results. We still don't completely understand how it works. It happens so quickly. We understand what happens when we clean, but we don't understand what happens when we plate."

The researchers are attempting to design experiments "in order to isolate one parameter or another." Modeling gives the team a bit more insight with the use of computational fluid dynamics software. A related area of interest is the removal of nanometer-size particles using brushes, Busnaina says, questioning whether they can extend or modify the noncontact techniques. The researchers have conducted experiments "down to 100 nm, of course. But we plan to go down further. Modeling shows you can push it, actually" in the 700- to 850-kHz range.

As director of the Microcontamination Research Laboratory at Clarkson, Busnaina presented a post-CMP cleaning paper at the recent ASMC conference "about the mechanics of brush cleaning, how the brush takes particles off, and how we can control the different parameters to make sure that brush cleaning is more effective." When the brush surrounds the particle two parameters are involved, pressure and torque. Pressure is the distance between the brush and the wafer. "Microscopically, the brush is very elastic. When it comes to a particle, it engulfs it, and at that point a spherical particle would have a much larger contact area with the brush compared with the contact area between the particle and the wafer."

Water that comes from the brush, which returns to its original shape, makes it "very easy" to remove the particle. "Water that comes from the brush or outside the brush will easily knock it off. We're trying to look at the different parameters that affect it," such as changing the charge on the brush to make it negative or positive when required. Busnaina and his colleagues have worked with IBM for approximately a year on a project "looking at contact and noncontact post-CMP cleaning."

	Ludo Deferm
	Vice president of business development
	IMEC
	Leuven, Belgium

IMEC is probably best known for introducing the single-wafer clean alternative for the semiconductor industry's standard RCA clean. Years of work in optical lithography also have given the university-based consortium a reputation as a center of excellence in lithography, Deferm notes. The development of embedded ferroelectric memories is yet another success, which has led to additional research into integration of such memories. According to Deferm, long-term R&D in CMOS technologies with European foundries such as Alcatel Microelectronics has also enabled IMEC to transfer processes to Tower Semiconductor.

In October IMEC named nine major chipmakers as the first members of its new 157-nm lithography program. The consortium's goal in launching the program with ASML is to develop
production-worthy 157-nm lithography capability by 2003. The nine chipmakers are Intel, Motorola, AMD, Micron, Infineon, STMicroelectronics, Philips, UMC, and Samsung Electronics. International Sematech also will take part in order to develop a production-ready gate stack process with equivalent oxide thickness of approximately 1 nm. Silicon dioxide layers are between 3 and 4 nm thick in 0.18-µm processes, IMEC points out.

Deferm attributes IMEC's track record in process technology and device integration to close collaboration with its industrial partners, each of whom place resident researchers at the center. More than 400 companies and institutes from around the world participate in research at the center. The IMEC Industrial Affiliation Program (IIAP) "is a tight R&D cooperation scheme that allows industrial researchers to integrate into IMEC research teams focused on a specific advanced research program or technology area for at least one year. As part of this collaboration, the technology owned by IMEC can be transferred to the industrial partner."

The center offers services in 10 areas. In addition to 157-nm lithography process development, they include 193-nm optical lithography, ultraclean process technology, salicide technology, low-k materials and copper damascene, CMP, and object-oriented system-on-chip design. Deferm says IIAP partners have the advantage of getting an "early insight" into IMEC's strategic research, reduction of time to market, cost and risk sharing, cross-fertilization, and "enhanced" process tech transfer.

The center offers services in five areas. They are advanced ASIC design, either digital or mixed mode; low-cost fabrication of prototypes through the Euro-practice multiproject wafer service; electrical and physiochemical measurements and analysis; performance of process steps such as ion implantation, etching, and masking; and a dedicated color filter deposition service.

The center's operating budget of $100 million is "derived from agreements and contracts with the Flemish government, the EC, the European Space Agency, and semiconductor companies worldwide." Less than 30% of IMEC's total income comes from government grants.

Deferm believes that a growing demand for low-cost ICs with different functionalities on the same chip is forcing a "horizontal change in process technologies. More functionality has to be integrated in the core processes, such as embedded memories. IMEC is currently focusing on the integration of nonvolatile memories in standard CMOS processes. Integration of RF functionality is also a major trend . . . pushed by the increasing demand for compact, high-performance telecommunication systems."

As nanotechnology for future ICs advances further, the business development vp notes that the "predicted end of continued scaling of CMOS technology" has led IMEC to begin establishing nanoelectronics and molecular electronics programs. Yet another trend is the convergence of communication, consumer electronics, and computer products. "As a result, many more synergies can be observed for joint R&D with semiconductor companies all over the world."

	Peter Will
	Director, Distributed Scaleable Systems
	Information Sciences Institute,
	University of Southern California Los Angeles, CA

"We're working on all this good MEMS stuff with silicon, doing both surface micromachining and bulk micromachining," says Will of his research with the School of Engineering's Information Sciences Institute. Using oriented crystals with bulk micromachining, the researchers have "etched things like 'V' grooves and nice flat vertical surfaces." A little more than six months ago, the institute's EFAB MEMS project was spun off into a startup called Memgen headed by Will's colleague, Adam Cohen.

Unlike the silicon processes Will mentions, the spun-off EFAB process uses regular metal. "The EFAB lets you build true three-dimensional structures. You can build closed cavities, for instance." Working under a DARPA contract, Memgen is building a minuscule power generator that will make electricity by burning an "environmentally friendly fuel."

For more than five years Will and a team of researchers have also toiled in nanotechnology R&D, with results that approach the realm of science fiction fantasy. "We're using a scanning force microscope to move things as opposed to measure things." In a lab dedicated to micromolecular robots, USC researchers are trying to manipulate and deposit colloidal gold spheres measuring 5 ­ 10 nm. Gathered together, the spheres "look like a field of dots," Will says. "We can see . . . where these gadgets are and then push them together, fuse them using DNA technology, and move them as units. You can move them around and pile them up.

"There's a notion that we can make 3-D objects on demand," the research director continues. "So, if things go well--if the creek don't rise and the dog don't bite--you could build cavities to order, for instance. You could put drugs in the cavity." As one example, Will raises the possibility of encapsulating a cancer drug in this infinitesimal cavity, then breaking the DNA bonds "on command" in the blood stream to release the drug at a predetermined time. "You can imagine selectively encapsulating something and selectively decapsulating something."

A new nanotechnology development called quantum dots raises a number of intriguing possibilities, Will points out. "We're trying to build a computer that's beyond Moore's Law." Researchers manipulate the silicon crystals by design in order to build atom-size transistors. Measuring 2 to 5 nm, the dots surpass the lithography limits of current silicon processing technology. Researchers have already used the objects as tags in DNA research, Will notes. "You can attach them to a cell and fluoresce them to tell whether the cell is defective or not defective. We know how to manipulate the quantum dots. Instead of just tagging them for protection, we're trying to say that we can make a switch--a transistor--out of them."

An equally fascinating R&D development from a MEMS point of view is Will's work in high-end robots that configure themselves. The goal of ISI's CONRO project is to make a miniature reconfigurable robot that can perform reconnaissance, search, and identification tasks in urban, marine, and other environments. Such a robot "will turn from a snake to a spider, then back to a snake" and be capable, for example, of crawling under doors.

Such a device will need very small motors, note the research director. "We really need better motors and better actuators. We don't get a lot of force out of a MEMS actuator." Will believes there are "a lot of good things done in the MEMS field," including sensors, accelerometers, and "arrays of little cells. All kinds of marvelous things, but I'd like to see some more actuating, quite frankly."

Stiction and bearings present the usual sort of contamination problems in MEMS manufacturing, Wills says. "Tribology is unknown in this field. Any piece of dirt kills you. One of the big issues [with MEMS] is packaging." A pressure sensor, for example, must operate in an immediate environment that can be quite unkind. "Some of the measurement might be in a corrosive fluid. It's not the normal ambient," he adds.

Wills cites seawater as an example of the type of environment confronting MEMS devices, and by extension the researchers who are devising ways to cope with it. "It's not the normal silicon stuff," he stresses, adding that he'd like to delve more into "microcorrosion issues." Meanwhile, R&D in this area "may trickle down into semiconductors later. You don't dunk semiconductors into salt water. But you do have to dunk MEMS devices into salt water."

Metal winners Winners and judges of the SRC Copper IC Design Challenge share a toast after the awards are announced in late September. The three university-based winners were chosen from 44 entries submitted by 34 universities. Taking the $35,000 first-place award was the team led by Professor Ramesh Harjani of the University of Minnesota. The University of Florida team led by Professor Kenneth O took the $25,000 second-place award. The $15,000 third prize went to the Carnegie Mellon University team headed by Professor Gary Fedder. Pictured left to right are Gary Fedder, Carnegie Mellon; Ramesh Harjani, University of Minnesota; Brian Floyd, University of Florida; Ken O, University of Florida; Jeff Benzing, Novellus Systems; Leslie Faiers, SRC; Larry Sumney, CEO of SRC; John Damiano, North Carolina State University; Tony Mule, George Institute of Technology; Dale Edwards, SRC; and John Kelly, Novellus Systems. In addition to SRC, the contest's sponsors were SpeedFam-IPEC, Novellus Systems, and UMC. The objective of the contest was to spur students to create novel circuit architectures that could be used to speed up the introduction of new copper interconnect technology. Minnesota's winning design was titled "RF Front-end Design with Copper Passive Components." The cash prizes will be used for IC design education programs at the winning schools. UMC, the Taiwan-based foundry, built the winning designs. "We're very pleased with the results," says Dale Edwards, program manager of design sciences for SRC and coordinator of the copper challenge. Rick Hill, CEO of Novellus and a member of SRC's board of directors, instigated the contest. "He'd thought it'd be a good idea to spur interest in copper technology. At first we were leery," remembers Edwards, who is an AMD assignee to the North Carolina­based research consortium. "We said, 'How many people are going to enter this thing? What if we put out an announcement and only three or four universities apply?'" All three prize winners were "heavily technology related," Edwards crows. First and second place "were really close. There should have been a tie for a winner." CMU's entry for CMOS micromachined RF components is "a MEMS-type project." Edwards believes the contest's success will attract more IC design students to become interested in the latest copper technology. "SRC has two main products," he adds. "One is students; the other one is research."

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