Building Copperopolis II

Reducing edge and bevel contamination to help enhance copper process yields

Cindy R. Simpson, Motorola; and Tom Ritzdorf and Curt Dundas, Semitool

A side-selectable wet processing chamber shows promise as a method for removing wafer backside contamination and eliminating copper films on the bevel and edge of the wafer.

In the race to integrate copper interconnect structures into high-end semiconductor devices such as microprocessors, fast SRAMs, and ASICs, chipmakers are focusing on the rapid implementation of copper interconnect processes to facilitate high-volume manufacturing, achieve short cycle times, and reach aggressive yield targets quickly. As part of the efforts to realize the benefits of copper, the usable area of the wafer is being pushed to the limit by full-coverage seed layers and minimum-reach contact configurations. As real estate near the wafer's edge becomes more valuable for device production, contamination control of the bevel and edge-exclusion regions must be made a priority in order to avoid causing defects in downstream processes. While the edge and bevel areas previously have not been singled out as critical concerns in the defect reduction equation, the copper era necessitates a more active effort to remove contamination from these regions of the wafer as part of a yield management program.

Controlling Bevel and Edge Contamination

Several variables affect the successful integration of copper into the device manufacturing flow and subsequent high-volume manufacturing. One important defect reduction and yield management variable is bevel and edge cleaning. This factor was not as critical in aluminum-based interconnect technology because of the relative stability of films deposited on the bevel and edge region, as well as the low level of mobility of the contaminants that reside in that region. However, in the copper era, bevel and edge stability and contamination mobility are more problematic, necessitating an active and effective means of control and management.

The successful control of bevel and edge contamination will contribute to manufacturing success by leading to increased yields and improved performance of chemical-mechanical polishing (CMP) and other downstream processes. The integration of bevel and edge-exclusion region cleaning into the deposition platform provides an opportunity to reduce cycle time through a single-wafer cluster process approach.

Management of the wafer edge is an important concern sometimes overlooked in the integration of new processes, such as copper interconnects and low-k dielectrics. This region of the wafer must be considered, especially as unit processes increasingly interact.¹ For example, barrier- and seed-layer coverage at the edge can be critical in ensuring the success of the electrochemical deposition (ECD) process that follows, minimizing yield loss caused by copper migration and eliminating edge-related defects during the CMP process. Although the edge-exclusion area is usually not of primary concern, it is an important part of the process integration scenario, especially from the equipment and process flow perspectives.

The typical copper interconnect process deposits a tantalum nitride (TaN) or tantalum (Ta) barrier layer, covering the entire frontside and bevel of the wafer. A copper seed layer is then laid down with a small (2-mm) edge exclusion using an ionized plasma PVD system with a shadow mask clamp that defines the seed-layer edge exclusion. This technique produces a sloped copper edge and an area of discontinuous copper "islands" at the seed-layer edge, with exposed areas of TaN or Ta, as shown in Figure 1. Copper electroplating systems must then use an electrical contact that reaches far enough onto the wafer surface to provide seed layer with enough thickness to ensure electrical contact integrity. If the barrier-layer material is exposed to the copper deposition process, poor copper adhesion near the edge of the film can result. Because of this, not only must contamination be removed from the wafer backside, but any material at the edge of the wafer that may later flake off during handling, CMP, or metrology steps must also be eliminated.

 

Figure 1: Drawing of copper seed layer and exposed barrier with copper islands.

The copper interconnect process (with oxide or low-k dielectrics) is one example of a module in which the various unit processes interact, especially at the edge of the wafer. Etch processes can affect what materials are exposed at the edge, which is an important factor in the adhesion of subsequent layers. Typically, the diffusion barrier (which may also have an impact on adhesion) extends out to the edge and even around part of the edge bevel. The copper seed layer, however, may have an edge exclusion, which affects the positioning of the subsequent ECD process contact location. Since ECD processing deposits copper in both the x and y planes, any islands of seed copper would further plate and be quite nonadherent. This nonadherent copper film could lead to flaking in the subsequent CMP stage. Flakes that are deposited on the CMP pads would lead to scratching or might redeposit on the wafer, which would severely affect device yield.

The current industry trend is to maximize usable wafer area in order to increase the number of good die per wafer. One way to accomplish this is to use full-coverage seed layers, which allows the ECD electrical contact to move outward on the wafer as far as possible. This helps eliminate problems of ECD copper adhesion to exposed barrier material, but it also results in copper deposits around the wafer bevel that are not removed by the CMP process, as illustrated in Figure 2. If this exposed material is not well controlled, flaking and yield loss can occur, as discussed above.

 

Figure 2: Rendering of wafer with a full-coverage seed layer and processing steps leading to residual copper.

Recognizing the need to eliminate potential defects and minimize copper contamination in downstream processes, Semitool (Kalispell, MT) has developed equipment and processes to remove this unwanted material and clean copper contamination from the backside of the wafer. This article discusses the development of these processes and presents typical process results from a customer site evaluation.

Equipment, Tests, and Results

The company's Capsule wet processing chamber, illustrated in Figure 3, was developed as a side-selectable chamber capable of maintaining a controlled environment around the wafer. The chamber has a minimal chemical volume of <150 ml and can process either side of the wafer. Additionally, the unit does not depend on the fluid properties of the chemistry to achieve either a very controlled film or contamination removal. The chamber's self-cleaning function helps eliminate cross-contamination problems.

 

Figure 3: The Capsule wet processing chamber.

In developing the bevel etch process, two objectives were identified: the removal of backside copper contamination and the elimination of copper films on the bevel and front edge of the wafer within a controlled distance from the wafer's edge. The removal of metallic contaminants from the wafer backside helps prevent the spread of copper contamination through the robotic handlers and stages typically found throughout the fabrication process line. The removal of the films on the wafer edge and bevel eliminates the yield issues associated with the diffusion of copper through the substrate. For example, if the backside of the substrate does not have a barrier to copper migration and undergoes annealing or another high-temperature process, the copper could migrate into the device and ultimately cause failures. These cleaning requirements dictate that the chemistry completely remove contaminants at very low levels. Additionally, to achieve high throughputs and short cycle times, the chemistry must be capable of removing relatively thick copper films in process times of <1 minute.

Several chemical mixtures and chemistry sequences were tested in order to determine their efficacy for contamination removal.² Each chemistry was evaluated in terms of how well it cleaned a wafer backside, as measured by total x-ray fluorescence (TXRF). After suitable cleaning chemistries were identified, the etch rate of bulk copper was considered. Since short process times are desirable, a goal of >2 µm/min was chosen. Using wafers that had been contaminated with copper sulfate plating solution, the frontside of the wafers were cleaned and resultant copper contamination levels were measured using TXRF. The results depicted in Figure 4 show that two chemistries hold promise in removing copper below the targeted level of 1 x 10¹¹ atoms/cm². Both of these chemistries had the requisite removal rates on copper films to allow their use in the bevel etch process in a single-wafer process configuration. These chemistries were a dilute mixture of hydrofluoric acid (HF) and hydrogen peroxide (H_²O_²) in DI water, and a similar mixture of sulfuric acid, hydrogen peroxide, and water. Further testing determined that either of these chemistries would achieve acceptable process results.

 

Figure 4: Wafer-cleaning results, as measured by TXRF, for various chemical mixtures.

Chemistry choice is driven by process integration and fab-specific chemical-handling issues. An important consideration when using HF-based chemistry is any potential etching effect that it might have on barrier films at the edge of the wafer. Because of this consideration, the etch rate of the HF/H^₂O^₂ mixture on common barrier materials was evaluated. Etch was measured by comparing the sheet resistance (R^_s) uniformity map of an unprocessed wafer with the R^_s uniformity map of a processed wafer. Even with exposure times of up to 30 minutes, no etching was observed. Because of the disposal concerns some facilities managers have concerning HF/H^₂O^₂ and other HF-based chemistries, alternatives such as the dilute sulfuric peroxide mixture (DSPM) are sought. In any case, results have shown that either solution effectively removes contamination.

The ability of the bevel etch process to deal with backside contamination is seen in Figure 5, which shows that the copper left on the backside of previously contaminated wafers, as measured by TXRF, is similar to that on a clean control wafer. The wafer backsides were contaminated by immersion in acid copper plating solution, then processed in a wet-process chamber and measured by TXRF at multiple positions. An uncontaminated control wafer was included, with measured contamination at <1 x 10¹⁰ atoms/cm² of copper. As shown, the starting level of contamination was very high, near 1 x 10¹² atoms/cm² of copper. The wet processing reduced the contamination to <1 x 10¹⁰ atoms/cm² of copper. These results were gathered on the same TXRF system used throughout the experiments and have been reproduced.

 

Figure 5: Backside cleaning results, as measured by TXRF.

The appraisal of the process's ability to remove copper at the edge of the wafer included an evaluation of the edge of the copper film that remains, as well as the concentricity of the copper film edge with respect to the wafer edge. Figures 6 and 7 depict the smooth edge that results from the bevel etch process. Figure 6 shows that the film edge is very smooth and not affected by discontinuities at the wafer edge, such as a notch or a scribe. The film edge can be controlled because the process is regulated by the chamber configuration rather than by surface tension and other fluid properties.

 

Figure 6: Photo of etched edge at wafer notch. Notice how the etch is not affected by the notch.

Figure 7: SEM cross section of an etched edge, showing transition from cleaned area to full thickness seed.

Figure 7 is a SEM cross section of the copper film produced by the bevel etch process, showing a smooth edge that has a very small dimension from full film thickness to complete removal. This example comes from a wafer that underwent a standard bevel etch process cycle. A 10-µm transition area from the cleaned edge-exclusion area to full film thickness was seen, with no undercut.

The bevel etch process also results in very clean wafers because of the controlled environment of the chamber. Since the chamber features a self-cleaning function, there is little or no cross-contamination, contrary to what is seen in typical single-wafer wet processing units where the chamber walls may capture chemicals during the process that are then redeposited in a subsequent process cycle. Results can be seen in Figure 8, which plots the postchamber in-film particle results for a 10,000-wafer marathon. Therefore, the wet process used in these tests demonstrated no residual contamination and yielded acceptable particle results.

 

Figure 8: Wet processing chamber in-film particle results.

Conclusion

In the race to increase manufacturing yields in copper interconnect processes, the management of contamination on the wafer bevel and edge has become increasingly important. The development and deployment of the copper bevel and edge etch process described here is just one example of how a potentially damaging variable can be controlled or eliminated, thus helping to maintain process yields. Understanding the interactions of unit processes, not only in the active areas but at the wafer edge, is necessary for the successful integration of copper into the device fabrication flow. Through experiments with alternative chemistries and the use of an available process, acceptable and repeatable results in controlling contamination at the bevel and edge region of a wafer were achieved. The integration of cleaning with the copper deposition process results in a manufacturing-friendly platform that contributes to the objectives of high-volume manufacturing, reduced cycle time, and high yields.

References

1. P Geraghty and J McInerny, "Using Exclusion Ring Technology to Avoid CVD Tungsten Bevel Contamination," MICRO 18, no. 7 (2000): 91­99.
2. C Dundas et al., "Characterization of a Novel Method of Cleaning Wafer Back Sides and Effecting a Bevel Etch in a Single Processing Module," in Proceedings of the Advanced Metallization Conference (Warrendale, PA: Materials Research Society, 1999), 173­174.

Cindy R. Simpson, PhD, has recently taken a position in logic device engineering for Motorola's Digital DNA laboratories. Since joining Motorola in Austin, TX, in 1992, she has been an assignee in the interconnect division of Sematech and the copper plating group leader in the company's Advanced Products, Research and Development Laboratory (APRDL). Simpson received a BS in chemistry from the University of Michigan in 1981 and a PhD in electroanalytical chemistry from the University of Colorado in 1986. She then joined IBM in Endicott, NY, in the printed wiring board R&D facility. (Simpson can be reached at 512/933-3184 or cindy.simpson@motorola.com.)

Tom Ritzdorf is director of ECD technology for Semitool in Kalispell, MT. He is responsible for process development for electrochemically deposited metals, including copper, for the semiconductor and associated industries. He has worked for the company since 1992. Ritzdorf has an MS in chemical engineering from the University of Minnesota and has 13 years of experience in the microelectronics industry, specializing in electrochemical deposition. (Ritzdorf can be reached at 406/752-2107 or tritzdorf@semitool.com.)

Curt Dundas is a process engineer at Semitool, where he is responsible for copper cleaning and ECD processes. He joined the company in 1997 and has since been involved in process development and implementation, with a focus on copper ECD. He received a BS in chemical engineering from Montana State University, Bozeman. (Dundas can be reached at 406/752-2107 or cdundas@semitool.com.)

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