Defect/Yield Metrology

Tracking STI using an advanced optical metrology algorithm

Douglas Schramm and Dale Bowles, Micron Technology; and Martin Mastovich, Paul Knutrud, and Anastasia Tyurina, Schlumberger Semiconductor Solutions

A new algorithm compensates for the variations and asymmetry introduced by the CMP step in the shallow trench isolation process.

Memory devices, such as DRAMs, have traditionally been manufactured using the local oxidation of silicon (LOCOS) process to achieve electrical isolation between memory cells. However, the method's creation of unused areas places serious limitations on its use in the deep submicron regime of next- and future-generation devices.¹

One industry response to this limitation has been the adoption of shallow trench isolation (STI), but obtaining reliable measurements after STI and chemical-mechanical planarization (CMP) is problematic. The intent of CMP is to minimize topography across a wafer; however, a certain degree of topography is essential for edge contrast in optical overlay metrology.² For example, conventional measurement optics require step heights >50 Å to provide sufficient signal and contrast for the system's algorithms to function properly, but advanced CMP processes can result in step heights of <20 Å.³ CMP further complicates the measurement task by causing significant variation in step height and film thickness (contrast), as well as by introducing asymmetry across a single overlay measurement target.⁴

The CMP process has nevertheless been used successfully on metal interconnect layers for some time. In that application, the relatively high contrast of the metal layers compensates for the low topography, so that enough optical signal is supplied to the metrology tool for adequate measurement. In front-end CMP processes such as STI, however, the registration marks are much more difficult to observe. Robust broadband optics with spatial filtering can improve the contrast of an image, but the granularity of the substrate, the variation in edge detail, and the asymmetry of the registration mark can overwhelm a standard measurement algorithm and significantly decrease the precision, accuracy, and success rate of the measurement process.⁵

To meet this challenge, a new algorithm has been created for use with the IVS 130 optical metrology tool from the Verification Systems group of Schlumberger Semiconductor Solutions (Concord, MA). After reviewing the LOCOS and STI processes, this article focuses on this new algorithm and its use at Micron Technology. Measurements from multiple production lots are provided to show that the STI process is running under control at the fab and that the new algorithm offers a significant advantage over the standard measurement process.

LOCOS Versus STI

In the LOCOS process, electrical isolation between memory cells is accomplished by growing a thick oxide in the interstices, which creates profiles that include wasted space. The first step in the process is to deposit a nitride film on the wafer on top of a thin oxide buffer film. This film is then etched out of the desired isolation areas but left in the active-cell areas to block the local oxidation of the silicon. Oxidation is carried out in a high-temperature, high-humidity diffusion furnace. During this step, a thick oxide grows in the areas not covered by nitride, and the oxygen diffuses down to the oxygen-silicon interface, where it reacts with the silicon to form SiO^₂, thereby creating raised profiles. While this oxidation in the vertical direction is desired, horizontal oxidation is not, since it results in oxide growth under the edge of the adjacent nitride, which creates a sloped region on either side of the raised profiles, as illustrated in Figure 1. Often referred to as bird's beak regions, the slopes are wasted space because the oxide is too thick to be an active part of the memory cell and too thin to be part of the isolation mechanism. Although they have no function, these regions exist around every memory cell of devices manufactured using LOCOS.

 

Figure 1: Cross section of an isolation barrier created using the LOCOS process. The sloped "bird's beak" regions are wasted space.

In contrast, the STI process eliminates this wasted space, allowing a decrease in chip size. The STI approach to creating electrical isolation is simple: cut a trench, overfill it with oxide, and use CMP to remove the excess. As shown in Figure 2, a trench is etched into the silicon and an oxide film that is thicker than the trench is deposited in it. CMP is then used to nearly flatten the surface and remove any protruding oxide.

 

Figure 2: Cross section of a wafer during the STI process; the raised oxide profile will subsequently be nearly flattened by CMP.

CMP is a very critical process step, because the memory cells are very sensitive to any scratches or other surface damage. Yield loss from CMP problems can be very high. The uniformity of the CMP process can also be difficult to control, which may impair the visibility of the edges of the features on the chips during later metrology steps. In many cases, the registration targets used to measure the optical overlay are nearly invisible after CMP is performed.

Measurement problems are particularly prevalent when an opaque film has been deposited on the wafer. Such films act as mirrors, preventing optical systems from "looking" through the film and "seeing" the topography from the previous patterns. A combination of low topography and mirroring can not only prevent optical overlay metrology tools from functioning but can also contribute to feature alignment uncertainty and potential yield loss.

Meeting the Challenges of STI Metrology

The short-term solution to the STI metrology challenge adopted by Micron Technology was to pattern and etch the opaque material off the registration targets before performing the photo steps for that level. This patterning and etching created images of the targets that were high in contrast and similar to those from the LOCOS process. However, this technique involved using an extra reticle and required seven extra process steps: priming, coating, exposing, developing, etching, dry stripping, and piranha cleaning. Because these process steps were time-consuming and costly, Micron has been collaborating with Schlumberger to develop a new algorithm for an overlay tool that is capable of measuring very faint images.

Optical Filtering. The first requirement for such a tool was the use of an optical spatial filter to enhance the quality of the image prior to measurement. Without such filtering, there would not be enough signal for any algorithm to be successful. Figure 3a shows the unfiltered image of a registration target; although the measurement locations have been digitally enhanced, there is not enough contrast in the image to find the edges. In comparison, Figure 3b shows an image of the same target with an automatic spatial filter integrated into the metrology tool.

 

a	b
Figure 3: Unfiltered optical image (a) and filtered optical image (b) of a registration target used for post-STI metrology.

The Effects of Asymmetry and Variation. Obtaining reliable measurements of STI layers, however, required more than the adoption of an advanced optical design. Because of the asymmetry of the targets and site-to-site process variations, the standard methods for edge detection were not effective in the STI production environment. Three major problems had to be overcome. The first was that measurement success rates were as low as 50% for some lots. Thus, many lots were being passed without enough measurement results to provide a significant and well-rounded sample. The failures would often be at the edges of the wafer, skewing the resulting data to the center sections of the wafer. The second problem was poor precision. Variations from lot to lot were causing unacceptable process control variability. Finally, using the standard algorithms to measure asymmetrical targets induced accuracy errors attributable to sample-induced shift, which is an overlay metrology error caused by the sample rather than by alignment variations or tool error.

An example of the site-to-site variation created by subtle changes in the oxide thickness from the STI process can be seen in Figures 4 and 5. Figure 4 shows images of two sites from the same wafer, while Figure 5 presents cross sections of the profiles from the boxed areas in those images. A comparable image and profile from a LOCOS-processed wafer are provided in Figure 6. Current algorithms rely on the consistent edge positioning, polarity, contrast, and detectability shown in this latter figure. The STI process does not provide this kind of consistency, which causes the standard algorithms to fail. The ratio of peak to background noise in STI measurements varies greatly, and the ratio of edge peaks may also change, shifting measurements to a different set of lines. The result, with most basic algorithms, is "false" measurements that appear to be correct.⁵

 

a	b
Figure 4: Images of two registration targets from the same wafer, showing site-to-site variation following STI processing.

a	b
Figure 5: Profiles of the boxed areas in Figure 4a and b, respectively.

a	b
Figure 6: Target image (a) and profile from the image's boxed area (b) from a wafer processed by the LOCOS method.

Algorithm Development. Because the standard algorithms are not capable of making the required measurements on the STI process layer, a new algorithm was designed to account for and be insensitive to the site-to-site variations typical of the process. Safeguards were also included that measure site uniformity and determine when a site should not be measured because of excessive sample-induced shift. Although such sites are not common, improper measurement of these features could cause fliers in the data and require remeasurement of the sample or analysis by a process engineer.

The key to successful metrology is to measure the parameter that the tool was designed to test and to be insensitive to all other process variations. Therefore, the mandate for the new algorithm was to find the edges of the STI box-in-frame feature, however they appear, and consistently measure them. The granularity of the substrate had to be overcome, since it can influence edge detection. Although optical image filtering enhances edge visibility, it can also enhance the prominence of granularity. The algorithm thus needed to be as robust as the standard ones, but it had to be more flexible in determining edges, positioning such edges, and filtering the image without enhancing the granularity of the substrate. Most importantly, the algorithm needed to make accurate measurements.

To meet these requirements, the algorithm considers both sides of a site simultaneously. The top- and the bottom-gated areas are considered together, as are the left and right. The algorithm seeks edge structures that are present on both sides. These edges must have symmetry while matching the predetermined edge structure in the setup. Once a symmetrical structure is identified, it is used to verify the center calculations of the algorithm. This allows for significant process variations as long as they occur symmetrically on a given site without sensitivity to that process.

The process of algorithm development was an iterative one that required a great deal of cooperation between Micron and Schlumberger. All data, good and bad, were shared to attain the desired goals. During initial tests, success rates indicated that the first algorithm enhancements implemented were working. After further testing, however, success rates, precision, and accuracy would frequently change as a result of lot-to-lot variations and continuing improvement of the STI process. Adapting to these changes led to steady improvements in the algorithm and enhanced diagnostics, as well as the monitoring of systems measurements. As process conditions were tuned for improved device performance, the algorithm parameters needed to become more flexible to accommodate the changes. Finally, testing on production wafers with changes in process flows and variations from lot to lot verified that the modifications in the algorithm made the metrology tool process-capable for STI.

Experimental Data

To validate the capability of the new algorithm and compare its results with those of standard algorithms, an experiment was performed on seven STI-processed production lots. Each lot was measured 10 times using a standard algorithm and the new algorithm, and the 3standard deviation was determined for each measurement site. These data were then averaged to achieve a single standard deviation for each lot for each measurement direction. The data presented in Figure 7 indicate that the x and y overlay registration measurements using the new algorithm were 2.4 times more precise than those with the standard one, bringing the metrology results within production tolerances.

 

Figure 7: Comparison of the overlay registration measurement precision of the standard and new algorithms.

The measurement success rates with the two algorithms are given in Figure 8. The new algorithm was shown to be superior in target edge detection at the wafer edge, and its success rate percentage was more consistent.⁵ The nonmeasurement of features that had been a major problem with the standard algorithm was virtually eliminated by implementing the new one.

 

Figure 8: Measurement success rates for the new and the standard algorithms.

In addition to the seven-lot validation study, a large sample of statistical process control data was collected over several months to demonstrate that the STI process is in control. Figure 9 shows the x and y overlay registration minimum and maximum values for 200 lots of DRAM product at the STI metrology step. The upper and lower control limits, which are determined by the requirements of the overall process, have been tightened by 25% since the introduction of STI to improve yield. These data demonstrate that the STI metrology algorithm is not only able to meet the requirements of a short-term experiment but also satisfies production needs over the long term.

 

Figure 9: Minimum and maximum x and y values for 200 production lots at the STI metrology step. These data indicate that the process is in control.

Conclusion

Since major improvements in a fab's process flow are not everyday occurrences, it is significant that Micron Technology is running its STI process with seven fewer steps than were previously required, thereby saving both time and money. This capability was made possible by the development of a new metrology algorithm that was designed to compensate for the asymmetry and site-to-site variation typical of STI processing. The data presented here demonstrate that the STI process can be measured not only in the controlled environment of a short-term experiment but also in the production environment over several months. The development of the new algorithm was an iterative process, which will continue as device features continue to shrink, creating new challenges in optical metrology.

References

1. J Warren, "Leaping into the Unknown with 0.18 µm," Semiconductor International [on-line], September 1998; available from Internet: http://www.semiconductor.net/semiconductor/ issues/issues/1998/sep98/docs/feature6.asp.
2. A Shchemelinin, E Shifrin, and A Zaslavsky, "Basic Challenges of Optical Overlay Measurement," in Proceedings of the SPIE 3050-29, Metrology, Inspection, and Process Control for Microlithography XI (Bellingham, WA: SPIE, 1997), 425­433.
3. N Sullivan and J Shin, "Overlay Metrology: The Systematic, the Random and the Ugly," in Proceedings of the Conference of the American Institute of Physics 449, Characterization and Metrology for ULSI Metrology (College Park, MD: AIP, 1998), 502­512.
4. A Mathai and J Schneir, "High-Resolution Profilometry for Improved Overlay Measurements of CMP-Processed Layers," in Proceedings of the SPIE 3332, Metrology, Inspection, and Process Control for Microlithography XII (Bellingham, WA: SPIE, 1998), 182­191.
5. D Schramm et al., "Algorithm Implementation and Techniques for Providing More Reliable Overlay Measurements and Better Tracking of the Shallow Trench Isolation (STI) Process," in Proceedings of the SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII (Bellingham, WA: SPIE, 1999), 116­122.

Douglas Schramm is an area coordinator at Micron Technology in Boise, ID, working in the stepper and metrology areas. Before joining the company in 1989, he worked as a photo engineer at Signetics, a division of Philips Semiconductor. Schramm holds one patent, Photo sensitive polyimide coating solvent prewet for reduced polyimide usage, which was disclosed in 1998. He received a BS in chemical engineering from Brigham Young University and an MBA from Boise State University. (Schramm can be reached at 208/368-3473 or dschramm@micron.com.)

Dale Bowles has been with Micron Technology in Boise since 1990 and is an engineer in the photolithography area. Previously he was at Intel and GTE Laboratories. He received a BS in microelectronics from Arizona State University in Tempe. (Bowles can be reached at 208/368-3014 or dbowles@micron.com.)

Martin Mastovich is an applications engineering manager in the marketing department of the Verification Systems group of Schlumberger Semiconductor Solutions (Concord, MA). Before joining the company in 1996, he was an XRF/EDX marketing applications specialist at Kevex Instruments, part of Fisons Instruments, and an SEM/EDX applications specialist at Noran Instruments, both of which are divisions of Thermo Spectra. Mastovich has also worked as a microscopist and served as president of the Philadelphia Society for Microscopy. He received a BS in geology from Dickinson College in Carlisle, PA, and later participated in the geology masters program at Emory University in Atlanta. (Mastovich can be reached at 978/318-4049 or mmastovich@concord.tt.slb.com.)

Paul Knutrud is director of marketing in the Verification Systems group of Schlumberger Semiconductor Solutions. In 1983 he joined Interactive Video Systems (IVS), where he was manager of the applications group responsible for optical overlay and CD SEM metrology systems. When Schlumberger ATE merged with IVS in 1997, Knutrud transferred to the marketing group, where he served as evaluations manager and applications engineering manager. He received a bachelor's degree in business administration from Babson College in Babson Park, MA. (Knutrud can be reached at 978/318-4041 or pknutrud@concord.tt.slb.com.)

Anastasia Tyurina has worked with the Verification Systems group of Schlumberger Semiconductor Solutions since 1997 doing algorithm development for metrology and other applied mathematics. Previously she was at Parametric Technology, where she was a software engineer for the manufacturing geometry group. She has an undergraduate degree in mathematics from Moscow State University in Moscow, Russia, and an MS in mathematics from Ohio State University in Columbus, where she is working on a PhD. (Tyurina can be reached at 978/318-4072 or atyurina@concord.tt.slb.com.)

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