Managing reticle quality for subwavelength lithography

Ingrid B. Peterson, Art D. Klaum, and Ed Hou, KLA-Tencor

RQM aids in the understanding of reticle defect printability and optimizes return on investment by creating a reticle-sampling plan that takes into account device production parameters.

As deep ultraviolet (DUV) lithography becomes more common in the manufacturing of semiconductor devices at 0.18-, 0.15-, and 0.13-µm design rules, detecting and evaluating mask defects will become increasingly crucial. With the advent of the advanced re-ticle enhancement techniques used for low-k₁ lithography, a defect on the reticle can have a significantly magnified impact when transferred to the wafer, a relationship expressed by the mask error factor (MEF). Consequently, finding, understanding the printability of, and quickly eliminating reticle defects will assume greater importance as lithography processes develop and design rules continue to shrink.

Reticle quality management (RQM), a reticle inspection methodology based on a suite of tools and software from KLA-Tencor (San Jose), involves a two-fold strategy for ensuring image quality in DUV lithography:

• It optimizes the return on investment of reticle inspection by implementing a reticle-sampling plan that takes into account important device production parameters.
• It aids in the understanding of reticle defect printability.

The first case study of the RQM system presented here concentrates on an analysis of focus exposure matrix (FEM) measurements from product and test wafers. This analysis illustrates the effects of marginal reticle defects on the process window. By analyzing FEM measurements, process engineers can quantify the process window after lithography patterning and etch and then compare the results for product wafers to lithography defect printability simulations. These simulations can decrease the time to results in fab production by accelerating the decision-making process.

One of the essential components of RQM is its ability to connect reticle and wafer defect coordinate data. To illustrate the importance of connectivity in the RQM methodology, case study 2 discusses the impact of reticle defects on yield, focusing on translation software that links the defect locations on reticles to those on product wafers.

Using a Reticle-Sampling Plan to Decrease Costs

The ability to predict, identify, and catch reticle failure is a critical factor in semiconductor manufacturing. Because overlooking a reticle failure can be catastrophic, it is imperative to establish an effective inspection plan that will reject a reticle before a defect condition develops into a reticle failure, or as soon as possible after a failure occurs.

The costs associated with an inspection plan are composed of material-at-risk and inspection operations costs. The RQM methodology calculates material-at-risk costs by using a failure impact­failure frequency model and by determining how quickly a given inspection plan can catch a failure and stop risking more material. An optimal inspection sampling plan that reduces material-at-risk costs is realized by allocating fixed inspection capacity more intelligently while inspection costs remain fixed. Moreover, the optimal amount of inspection capacity and its allocation can be calculated so that the overall cost is minimized.

To achieve an optimal reticle inspection plan, an analysis method was established that correlates reticle characteristics with failure times. As a result of this correlation, groups of reticles with similar characteristics and failure times are established. This method allows technicians to include reticles with little or no historical data in the inspection planning if their characteristics correspond to the established reticle categories.

By estimating reticle failure rates and failure impacts for the reticle groups in question while including financial and fab information (wafer starts per week, number of dies per wafer, and average selling prices), optimal reticle inspection frequencies can be established. The stochastic model can then output costs for different inspection plans, enabling the choice of the optimal inspection plan. For example, if the data for reticles A, B, and C have different values for three important components, the magnitudes of these components affect the inspection needs of the reticles. Thus, if reticle A is responsible for greater losses than reticles B or C, the optimal inspection plan calls for increasing the inspection frequency of reticle A at the expense of B and C. This trade-off is necessary since overall inspection capacity is fixed.

RQM also allows for the optimized implementation of a reticle inspection strategy to minimize yield loss in fabs that produce multiple device types. For example, a single defect can cause a 10% yield loss if it appears on a 10-die reticle or a 50% loss if it appears on a 2-die reticle. Also, defects on noncritical levels of the reticle set may not impact yield as much as defects on critical levels. Therefore, sampling all reticles at the same preset frequency is not a cost-effective sampling strategy. Instead, different inspection sampling plans for different reticles and layers lead to more economical reticle quality management and higher yields.¹

Case Study 1: Using RQM to Detect Marginally Printing Reticle Defects

Reticle quality management consists of two types of reticle inspection: incoming quality checks (IQCs) and reticle requalification. Figure 1 illustrates a suggested RQM sequence for performing incoming quality checks.

 

Figure 1: Flowchart of a typical RQM process.

Reticle requalification is predicated on the need for periodic reticle inspection, since reticles are known to start printing new defects at unknown points in time, impacting product yield. Reticle requalification relying on advanced reticle inspection tools has become an important method for reducing yield risk from reticle defects caused by such mechanisms as particles, electrostatic discharge (ESD), and crystal growth.

Investigation of a Gate Reticle. To investigate the effectiveness of the RQM system, a study was conducted to uncover the source and impact of marginally printing reticle defects on the lithography manufacturing process window of gate and contact 4x DUV reticles used to manufacture 16-Mb flash memory devices for a major U.S. microprocessor manufacturer. During yield analysis, several lots were found to have a reticle-site-dependent yield signature in which one production die (die 7 in Figure 2) resulted in a considerably depressed yield. It was suspected that a reticle defect was responsible for the repeated failures. Consequently, the IQC procedure was repeated for all the critical-layer reticles of this particular product. This procedure used the SL3 STARlight simultaneous transmitted- and reflected-light contamination inspection system to review all the critical reticles. In addition, in-line wafer defect inspection results for repeating defects were analyzed.

 

Figure 2: Results from the STARlight inspection of the gate reticle showing the location of the defects on dies 1, 2, and 5.

A detailed lithography investigation was launched while product engineering continued with end-of-line failure analysis and the chemical deprocessing of the affected die, whereby particular attention was paid to the sites suspected from the yield analysis. One repeating defect was located on the gate reticle, but this defect was not located on die 7 according to the sort results. Ultimately, the chemical deprocessing of the affected die revealed a subnominal contact feature that was marginally making electrical contact.

The lithography investigation consisted of test wafer inspections, focus exposure critical dimension analysis, and reticle defect printability simulations. In addition, reticle and product wafer inspections were conducted on all critical layers. Four defects on the gate reticle were discovered, as illustrated in Figure 2. The reflected-light images of these defects produced by the contamination inspection system are seen in Figure 3. The images indicated that all four defects were repair defects. Typically, repair defects are much more apparent in reflected-light images than in transmitted-light images and appear with a surrounding frame because of the staining done during the repair process.

 

Figure 3: Reflected images of defects on the gate reticle.

Once all the defects had been detected by the reticle inspection system, it was necessary to identify which of them printed. Since wafer defect maps at the poly resist patterning step and after the etch step on product wafers indicated no signature of a repeating defect between exposure fields, it was decided to expose resist-on-silicon test wafers with this reticle. This procedure, commonly referred to as image qualification, or "image qual," is frequently used as a lithography defect monitor and a qualification check for new reticles.

Image qual consists of applying patterned photoresist to a flat silicon wafer and subjecting the wafer to automated die-to-die defect inspection with a KLA 2132 wafer defect inspection tool. In this investigation, the inspection tool's image qualification sensitivity recipe was set at a much higher value than that commonly used for product wafer inspections. This can be done with resist-on-silicon wafers, with their much higher signal-to-noise ratio than that of topography product wafers. High noise levels caused by defects and color variation from underlying layers make product wafers less sensitive to inspection than image qual wafers.

The results of the image qual, shown in Figure 4, indicated that only one of the four defects printed. Since this defect was caused by a CD variation, the image qual wafer had to be slightly underexposed, resulting in a poor print that the inspection tool could readily detect. The defect inspection tool indicated that the printed defect corresponded to defect c in Figure 3, which was the lower defect in die 1 of Figure 2. As seen in the wafer map illustrated in the upper-right-hand portion of Figure 4, the position of the defect on the reticle was the same as that of the defect on the wafer (taking into account the mirroring factor).

 

Figure 4: Wafer defect map for gate IQC (left and upper right) and a CD SEM image of the reticle repeating defect on the IQC wafer (lower right).

Figure 5a is a transmitted-light image of this defect and Figure 5b a reflected-light image. After the defect was identified, the reticle was sent back to the mask vendor, where reticle SEM imaging (Figure 5c) determined that the stain in the reflected image was a repair. The circled area of this image indicates a faint stain, repair imprint, or contamination spot in the quartz area adjacent to the repaired chrome line.

 

Figure 5: Transmitted-light image (a), reflected-light image (b), and reticle SEM image (c) of gate reticle defect. The CD error was the result of a reticle repair.

Pass/fail criteria for defects are based on transmission loss. This defect possibly passed the light transmission disposition criteria for STARlight images at the fab and the mask vendor because of the differences in transmission loss at the printing wavelength of 248 nm compared to the transmission loss at the inspection system's wavelength of 488 nm. In addition, as the images in Figure 3 illustrate, it is very hard to predict which defect printed solely by analyzing the reflected images. In fact, further investigation and analyses of all four defects indicated that defects b and d in Figure 3, which look worse than defects a and c, had no impact on the CD process window or yield.

Determining a defect's printability is aided by printability simulation, an off-line method for predicting how features and defects on reticles print on actual wafers.^2,3 In this case, the reticle defect transmitted-light image in Figure 5a was input into photolithography simulation software. The simulation software then output aerial images with predicted resist contours, which were compared to wafer SEM images. While the differential CD (nondefective CD minus defective CD) of the defect from the aerial images was calculated to be 63 nm, the differential CD of the defect from the SEM image in Figure 5c was 69 nm. Aerial image focus exposure simulations showed a minimal overlap of the defective versus nondefective feature process window, with an approximately 50% reduction in process window size. These data were in excellent agreement with product and test wafer FEM CD measurements. Figure 6 shows the process window overlap determined by measuring the CDs on FEM test wafers after resist patterning. CD SEM measurements were automatically sent to a process window analysis software package to determine the process window.

 

Figure 6: Process window analysis software results of gate reticle patterning on test wafers shows CD process window overlap for defective and nondefective features.

A small process window overlap allows both defective and nondefective features to print within specification under optimal process conditions. In-line SEM images from product wafers were used to compare defective and nondefective gate pattern features at opposite ends of the focus spectrum under worst-case exposure conditions. Although the defect in question printed noticeably worse at positive relative focus, it did not appear to cause a poly bridge at resist patterning or after etch.⁴

After running the gate layer FEM, the product wafers received standard processing through the end of line. The wafers were then electrically tested to determine the functionality of the product die. Electrical test results indicated that although the functional process space for the defective die was reduced, a significant process window remained, confirming the results of CD FEM tests on product and test wafers, as well as printability simulation tests.⁴

Investigation of a Contact Reticle. While the gate mask investigation was in progress, strip-back analysis determined that the electrical failure was in fact the result of an undersized contact. As in the case of the defective gate, no contact reticle error was detected either before or after etch on product wafers. Moreover, the contact image qualification of a resist-on-silicon wafer printed with a contact reticle and inspected on a wafer inspection tool did not detect this defect initially. With the aid of bitmap coordinates and SEM images from strip-back analysis, the wafer inspection tool's recipe was optimized to achieve the highest level of sensitivity. The high-sensitivity recipe, however, could not be used to inspect product wafers because of excessive background noise, as explained in the discussion of the reticle gate defect.

Figure 7 presents a defect map from the wafer inspection tool set at the high-sensitivity recipe showing a repeater defect for a contact image qualification wafer. The defect is a CD error, a single undersized contact on the reticle. Since this was neither a repair nor a particle defect, the STARlight was unable to detect it because the tool lacks a die-to-die comparison feature. Consequently, the reticle was inspected on a KLA353UV die-to-die inspection tool, which easily detected the undersized contact, shown on the left in Figure 8.

 

Figure 7: Wafer defect map for contact IQC (left and upper right) and an image showing an undersized contact (lower right).

 

Figure 8: Defect image from die-to-die inspection tool (left) and the contact defect simulation results from simulation software with resist model (right).

The CD differential between defective and nondefective contacts was simulated using three different lithography simulation software packages. The results of the Finle Prolith package (which includes a resist model) best matched wafer CD SEM measurements. While the differential CD of the resist model was 110 nm, the CD differential calculated from the product wafer SEMs was 109 nm, as shown in the right-hand side of Figure 8. Two other lithography simulations based on the same aerial image used in the Prolith simulation yielded CD differentials of 73 and 65 nm, respectively.

Further process window comparisons of the contact were made using Prolith. Simulation results showed no process window overlap. Product and test wafer FEM results also showed no process window overlap for defective and nondefective features. After undergoing FEM analysis, the product wafers received standard processing through the end of line. The wafers were then electrically tested to determine the functionality of the product die. The results of electrical tests on the contact, in contrast to those performed on the defective gate, showed no allowable process window for this reticle error. Once again, product, test wafer, and electrical test results were in excellent agreement with one another.⁴

Linking Reticle Defects to Wafer Defects

To complete the optimization of an RQM plan, adequate reticle defect data and analysis are required to estimate failure time distributions for the main reticle types. Until recently, no easy-to-use tool was available to correlate reticle defect locations to wafer defect locations. Such a tool is needed to perform the analysis of reticle defect printability. By driving from the reticle to the wafer to find common defect locations for review, the X-Link translation software module from KLA-Tencor addresses RQM's need for defect correlation. This software can translate reticle defect coordinates into equivalent wafer defect coordinates so that defects on reticles can be connected to defects on wafers. Rotation, mirroring, and reduction ratios are all accounted for in the translation process. The translation software generates standard KLA results files (KLARF) that can be loaded on many different metrology tools for wafer defect review.

Although reticle quality management is intended primarily for IQC and reticle requalification, it can also assist in analyzing device failures and determining process window shift. When a reticle is due for inspection, it is placed in the queue to be worked on. If no defects or printable defects are found, the reticle is sent to the lithography area. If the reticle contains defects of concern, the translation software is used to create a KLARF, which is then used to drive to the potentially defective sites on a test, FEM, or product wafer to verify whether a particular defect printed. To verify photo process windows, process simulations can be run by inputting images provided by the translation software. Finally, the KLARF from the translation software and the KLARF from the wafer inspection tool can be imported into KLARITY and compared so that only matching defects will be displayed.

Case Study 2: Using RQM to Demonstrate Defect Printability

An investigation into a repeating defect on a 16-chip (4 x 4 array) SRAM reticle set at a major U.S. ASIC manufacturer highlighted that an effective RQM program using the translation software module can demonstrate the printability of a defect. Although the device was being built to prove the effectiveness of 0.25-µm process technology and design functionality, the opportunity to verify the reticle defect printability process was quite valuable. Generally speaking, RQM seeks to prevent yield losses from reticle defects before they appear. This investigation, in contrast, was initiated as a result of a device failure. The flow chart in Figure 9 outlines the steps in the printability verification process.

 

Figure 9: Printability verification flowchart.

Although it was suspected that the poly-silicon layer had a missing gate, all the critical layers of the reticle set were inspected with the transmitted- and reflected-light inspection system. While many interesting defects were found on the pattern, pellicle, and glass surfaces, the primary defect of interest, depicted at left in Figure 10, was the outline of the original pattern with some chrome remaining on the top. In addition to this defect, several repair sites were found, as illustrated in Figure 11. The general location of the reticle defect fit the location of the device failure.

 

Figure 10: Image of missing gate on a reticle (left) and the same defect after it has been transferred to the wafer (right).

 

Figure 11: Image of repair site defect (left) and the same defect after it has been transferred to the wafer (right). The affected feature was 106 nm wider than the surrounding patterns.

The purpose of this study was not just to find the defect, but to implement a highly repeatable process for driving to the site of potentially defective regions. As has been demonstrated, an effective RQM program can aid in verifying the printability of such potentially defective sites prior to the release of reticles to full-volume manufacturing. The use of RQM can also be extended to facilitate the determination of process window reductions.

A critical step in setting up the data translation process is to establish the physical coordinates of the defects on the reticle as well as the physical and optical relationships between the reticle, the stepper, and the wafer. This information is then transformed into the reference frame coordinates of the stepper and, finally, the wafer. The file in X-Link that contains this information is called the Profile. Figure 12 shows the Profile data entry screen, with values for the investigation under review.

 

Figure 12: Screen capture of the translation software's parameter entry window.

Following the generation of the wafer KLARF and its transfer to the wafer review SEM, this tool was used to drive to the defective sites on the wafer. After some customization of the Profile parameter requirements, the tool drove to within a few microns of the defect sites. At 5000x magnification, the display window on the SEM was approximately 30 x 40 µm and the defects were fairly close to center. The printability of the defects is demonstrated by the right-hand images in Figures 10 and 11.

Conclusion

As subresolution lithography processes become more aggressive and demanding, reticles must be monitored to catch potentially drastic yield hits. Furthermore, because semiconductor devices are being manufactured with increasingly advanced design rules, previously unimportant reticle defects can now cause yield-limiting defects on product wafers. Consequently, there is a growing need for new methods that rely on statistically based methodologies to optimize reticle inspection capacity or frequency. RQM serves this purpose.

Translation software completes the defect information connection between reticle and wafer defects. It enables fast and easy characterization of reticle failures and the impact of defects for different reticle types. Defect case studies have shown the importance of the translation software for determining the printability of reticle defects‹an important component of RQM. Printability simulation software can provide fast time to results by improving dispositioning accuracy. In addition, simulation results from both gate and contact investigations were very encouraging. Indeed, in case study 1, dispositioning accuracy would have been much higher had the defects been simulated either with aerial image or resist model simulation software. In the absence of such software, both defects were manually classified as nonprinting defects.

Printability simulation can be combined with an optimal sampling strategy to increase the return on investment of reticle inspection. As shown in case study 1, printability simulation can decrease the engineering costs associated with printing wafers and performing SEM measurements, thus lowering costs that result from yield losses caused by allowing yield-limiting defects to pass reticle inspections.

The methods presented in both case studies can be implemented in different phases of RQM and reticle requalification. At the mask shop, for example, reticle inspections coupled with printability simulations based on aerial images can be the first inspection phase of RQM. Once the masks are received in the fab, defect inspection, resist model printability simulations, process window analyses based on these simulations, CD SEM measurements of defects considered marginal, and the use of translation software complete the RQM inspection process. Finally, electrically tested FEM wafers can identify additional process interactions and product sensitivities.

References

1. V Samek et al., "Cost Effective Reticle Quality Management Strategies in Wafer Fabs," in Proceedings of the 10th Annual Advanced Semiconductor Manufacturing Conference and Workshop (San Jose: IEEE/SEMI, 1999), 254­258.
2. D Pettibone et al., "Wafer Printability Simulation Accuracy Based on UV Optical Inspection Images of Reticle Defects," in Proceedings of the SPIE Symposium on Optical Microlithography XIII (Bellingham, WA: SPIE, 1999), 711­720.
3. I Peterson et al., "Investigation of Fast and Accurate Reticle Defect Assessment Methods using STARlight for Chrome-on-Glass (COG) Reticle Defects" (paper presented at Photomask Japan, Yokohama, April 2000).
4. J Erhardt et al., "A Defect-to-Yield Correlation Study for Marginally Printing Reticle Defects in the Manufacture of a 16MB Flash Memory Device" (paper to be presented at the Advanced Semiconductor Manufacturing Conference and Workshop, Boston, September 2000).

Ingrid B. Peterson, PhD, is solutions development manager for lithography and parametric module solutions at KLA-Tencor (San Jose). She joined the company in 1995 and has been an applications development manager for reticle inspection analysis products and a consultant for the firm's yield management consulting group. Before joining KLA-Tencor, Peterson was a staff process engineer in photolithography at VLSI, a staff research scientist at the Max Planck Institute for Solid State Physics in Stuttgart, Germany, and an adjunct assistant professor in the physics department at the University of California, Los Angeles. She received a PhD in physics from the University of California, Santa Barbara. (Peterson can be reached at 408/875-5491 or ingrid.peterson@kla-tencor.com.)

Arthur D. Klaum is a staff applications engineer for the photomask business unit of KLA-Tencor's reticle and photomask inspection division, a position he has held since joining the company in 1997. He supports the eastern U.S. region. Before joining the firm, Klaum held photomask and reticle engineering positions with General Instrument's photomask operation, Magnetic Peripherals's new product development group, Digital Equipment's advanced semiconductor development group, and Motorola's photomask operation. He received a BS in chemical engineering from Manhattan College in Riverdale, NY. (Klaum can be reached at 215/412-2683 or art.klaum@kla-tencor.com.)

Ed Hou is a senior applications engineer in KLA-Tencor's Rapid division. He has been with the company for more than four years and is currently working on the virtual stepper project. Hou has authored technical evaluations and conducted demonstrations of the division's equipment and is frequently called upon to be the utility infielder for the division. He has a BS in chemical engineering and an MPH in environmental sciences from the University of California, Berkeley. (Hou can be reached at 408/875-3493 or ed.hou@kla-tencor.com.)

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