Metrology sector seeks methods to measure up to new challenges

Metrology challenges facing the semiconductor industry will spur rapid growth and research in the sector, according to several participants in a recent international conference. These challenges will also stretch the capabilities of some current measurement methods and strain the industry's pocketbooks, they say. New metrology approaches discussed at the event may offer solutions for an industry confronting the deadlines and the red roadblock imposed by the International Technology Roadmap for Semiconductors.

"There is an exploding opportunity for metrology," asserts Peter Borden, CTO of Boxer Cross, a provider of in-line metrology tools. "That's very clear. What's driving this is the adoption of an entirely new set of material systems and methods in manufacturing. It's much broader than just copper. There are low-k dielectrics, and high-k gate dielectrics; and multiple films and opaque film stacks are being used in a lot of different places, not just interconnect. There are ultrashallow junctions. Plus, there are very significant opportunities in lithography." In the critical dimension area, "the need for getting 3-D information is growing," says Alain Diebold, a senior fellow at International Sematech.

Borden and Diebold were among the industry experts who presented papers at NIST's 2000 International Conference on Characterization and Metrology for ULSI Technology, held June 26­29. Sponsored by NIST's National Semiconductor Metrology Program, the biennial meeting in Gaithersburg, MD, drew approximately 250 participants.

Diebold offered an overview of the roadmap's impact on metrology. Examining several aspects of the roadmap, he addressed the effect of the accelerated introduction of technology nodes, as well as the timing of process tool introductions. Diebold also discussed the requirements for new materials, new processes, and new structures. "What I tried to indicate was that you can look at the roadmap in a few different ways, and I [pointed out] some of the useful ways to think about what the roadmap tells you," he says.

The impact of new device structures "beyond CMOS" was one aspect that Diebold took on. He noted that research into vertical transistors being conducted at companies such as Bell Labs will have a profound effect on measurement methods. "All metrology changes if you go to vertical transistors," he says.

Diebold explains that critical dimension (CD) methods for these new structures require measurement of film thickness "instead of a traditional CD-type measurement." Transistor gate dielectrics will be on the sidewall instead of on a "flat, planar area." In addition to the growing need for 3-D critical dimension information, there's a need for improved modeling in order to retrieve CD SEM data. New tilting, electron beam CD SEMs are also available.

Using scatterometry is another route the industry may take for CD measurement, he points out. "I think scatterometry is a pretty substantial possibility for CD measurement for very rapid line control." The in-line technique would act almost like a sensor, adds Diebold.

Improvements in CD SEMs involve trade-offs, though. For example, if you improve the resolution and change the beam voltage you lose depth of field, Diebold notes. "You get two improvements at the loss of other capabilities. Right now, the depth of field is getting worse and worse as people are improving the resolution. The question is, will CD SEMs lose so much depth of field that in the future you will face a lot of issues in getting three-dimensional information?"

In the front-end process area, the introduction of alternative gate-dielectric materials raises questions for tool providers. "What do you tell the metrology suppliers to do with their optical metrology tools? Are they good enough, or do you ask them to extend them into another wavelength range? Do you go to infrared or the other way, to UV? That's the question people like myself are working hard to answer: how to get optical models and new metrology for materials like high-k dielectrics."

Each new materials system represents a major risk for chipmakers, insists Borden of Boxer Cross. "The last thing AMD or Intel wants is for all their processors to fail three years after they release them because they overlooked something."

Both Borden and Diebold emphasize the growing importance of integrated metrology. The term refers to "using a cluster station on a cluster tool to do some measurements, or add something in the wafer intro port," says Diebold. "This is a very interesting approach, and it's the most active part of the whole advanced equipment control/advanced process control (AEC/APC) movement. For the longest time people were. . . focusing their main efforts on using sensors. Now they're saying, 'Let's take a step before that. . . and try to work the software in as we work on the process station."

Borden believes integrated metrology solutions "will make material handling and the 300-mm [transition] much simpler." He notes that suppliers have been taking "relatively classic metrology and repackaging it into modules. There's relatively little focus on integrating enabling metrology and coming up with something entirely new."

Diebold warns that roadblocks, compromises, and trade-offs lie ahead. "Do you want one central metrology tool with a lot of great capabilities? Or do you want a lot of stations on cluster tools to do the measurements but that maybe have fewer capabilities because they're less expensive?"

One of the unresolved issues remains open or closed architecture solutions, Borden says. "There's a movement where there's essentially Applied Materials and then there's everyone else. Everyone else is going to push open architecture, and then Applied is going to push an Applied approach."

Determining the right business model is a problem for integrated metrology suppliers, Borden points out. Because it's an OEM-based business and not a stand-alone business, profit margins become an issue. He says he's familiar with this business model issue, having been an executive with High Yield Technology. HYT was an integrated metrology company that he and his partners started approximately 15 years ago. "Part of the problem is that an integrated metrology supplier is at the tail end of the dog's tail that's wagging. The price of your product can't go up too high or the OEM customer will balk. They're not doing this to spend more money on metrology. They're doing this to spend less money on metrology. In today's business model, the integrators are getting the bulk of the money."

The issue presents a problem similar to the one the industry faces in making the move to 300-mm processes, Borden asserts. "A few years ago, IC makers were saying you have to have 300 mm. It's coming on strong, and you have to have it or you're not going to sell any tools. Now, in mid-2000, we're just starting to sell metrology tools. So we've had to bear all the development costs. If integrated metrology is like everything else in this industry, it's going to happen slowly over several years. Metrology tool suppliers may have to carry the cost of this development for a long time."

Boxer Cross can point to a success in the metrology sector. The paper Borden presented covers junction depth measurement using carrier illumination. The technique is used in the company's BX-10 source/drain and ultrashallow junction measurement system, one of which is installed at International Sematech. The tool enables in-line measurement of annealed dopant layers on product wafers. Work done at AMD has shown that the chipmaker "could make a measurement immediately after forming the source drain structures in the transistors. That measurement would predict the transistor performance at electrical test." The technique enables a chipmaker to measure a process step and have the ability to know "how those transistors will work at the end of the line.

"That's exciting," Borden continues, "because as far as I know, that's the first time for showing a direct correlation of an in-line measurement directly at the process step to an end-of-line electrical result. That's normally discovered three to four weeks later." The success of this type of technique could represent a major boost in profit per wafer for chipmakers such as AMD and Intel, both of whom are racing "to get the fastest microprocessor." So much has happened before electrical testing it's difficult to pin down the sources of nonuniformity at the transistor performance step. The technique will enable users to optimize uniformity, according to Borden.

Diebold championed the research of three other presenters at the conference, each of whom offered a different method for measuring the metal film thickness of a barrier layer or of the copper seed layer. Robert Stoner of Brown University presented a paper on a picosecond ultrasonic measurement method that uses a very short pulse of laser light directed onto the surface of a thin film of metal. The technique makes a noncontact measurement of the film thickness in approximately one second, Stoner says.

Another paper, presented by Michael Gostein of Philips Analytical, highlighted an optoacoustic metrology method for copper interconnects using impulsive stimulated thermal scattering. "It measures the thickness of fully patterned structures," says David Seiler, chief of NIST's semiconductor electronics division and conference coordinator. "It can be well suited for high-throughput use." Bill Johnson of Therma-Wave presented a third approach for copper barrier layer metrology, Diebold notes. The technology is based on in-line rapid x-ray reflectivity.

The biennial NIST conference is the third in a series. "It's unique in the sense that it brings together high-level people and people who carry out the work," Seiler says, adding, "In two years we will be involving more fab people. A lot of the metrology solutions are in analytical labs, but a lot of this information needs to be percolated into the fab." He called this year's confab "the best meeting we've had yet," an assessment based on "the many outstanding invited talks and the strong poster sessions."

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Many of the technical papers presented at the NIST 2000 International Conference on Characterization and Metrology for ULSI Technology are available for viewing at http://www.eeel.nist.gov/812/conference/talks2.htm.