Defect/Yield Analysis and Metrology

Implementing on-line ADC and an automated yield information management system

Frank Poag and Douglas Paradis, Texas Instruments; and Mahesh Reddy and Jon Button, KLA-Tencor

Data consistency and rapid response to yield-limiting defect excursions are among the benefits realized from the installation of automated data-handling systems.

When a wafer fab processes a large number of different logic devices at several technology nodes simultaneously, its defect-sampling strategy at any given time must focus on two types of devices: those with the most advanced technology and those currently being produced in the highest volume. This diversity of data challenges automatic defect classification (ADC) systems in several ways. Not only must the ADC classifiers be portable across different device types within the same technology node, but the classification data must also be analyzed quickly and efficiently to prevent yield losses caused by defect excursions. A strong yield management program that can react to both ADC and manually classified defect data is critical to the fab's continued success.

This article describes the implementation of on-line ADC together with an analysis module of the PMC-Net fab-wide yield information management system from KLA-Tencor (San Jose) at Texas Instruments's DMOS 5 wafer fab in Dallas. The benefits and challenges of the systems and the fab's payback analysis are discussed.

Wafer-Disposition Process Flow and Tool Set

Figure 1 illustrates the basic wafer-disposition process flow the DMOS 5 fab. Following the inspect-and-review step, which includes ADC at key levels, the statistical process control (SPC) system automatically holds any lots in which a defect excursion has been detected and constructs a queue for such lots. Each excursion event is then analyzed and a disposition decision is made based on the goal of containing the impact of the event. When it is determined that the SPC result represents a false alarm, the lots are sent on for further processing.

Figure. 1: The fab's basic wafer-disposition process flow.

The fab's yield management tool set includes Model 2138 bright-field microinspection systems, AIT dark-field microinspection systems, and Surfscan 6000­series unpatterned-wafer inspection systems (all from KLA-Tencor). These tools are used as process monitors for various types of equipment. Additionally, a KLA-Tencor 2132 system is used for photocell monitor (PCM) analysis. Defect review stations include a KLA-Tencor CRS confocal station, INS-2000 optical stations from Leica Microsystems (Allendale, NJ), and several scanning electron microscopes. Two separate systems are used for analysis: the yield information management system's Quest/Klarity database module and a system developed internally by the fab.

The components and flow of the fab's yield management program are given in Figure 2. All patterned-wafer defect inspection tools have onboard ADC. Data from these ADC modules are sent to the automation server and to the database module, which uses one of the data analysis systems to report the various results. Although the fab originally sent data from a few of the bare-wafer inspection tools to the automation server and then incorporated some of those data into the database module, this portion of the system has been disabled because the high data volume was causing overload issues; however, the capability still remains. The review tools also send images to the automation server, and when a review is finished, these files are delivered to the database module. The automation server initiates log-in and log-out functions via a proprietary system and forwards data to the fab's manufacturing execution system (MES) and other internal systems.

Figure 2: Data-flow diagram for the fab's yield management program. Components shown in color are part of the new yield information management system.

ADC Results, Benefits, and Challenges

The DMOS 5 facility typically uses the bright-field inspection systems at postetch, and it uses the dark-field inspection tools at chemical and physical vapor deposition steps and following chemical-mechanical polishing (CMP). Before implementing ADC, the fab undertook a major, ongoing effort to build classifiers for these inspection systems and the PCM tool, which is used to monitor deep-ultraviolet (DUV) lithography. Before a classifier is released for use with a process-monitoring system, the purity and accuracy of the ADC results must both exceed 80%. (In this context, purity is the ratio of correct classifications to the total number of defects detected in that class, and accuracy is the ratio of the number of classified defects detected to the actual number of defects of that type.) The inspection systems' ADC purity and accuracy continue to be monitored, and whenever they drop below 70%, an engineer is dispatched to reoptimize the classifiers.

Examples of some purity and accuracy measurements performed on a dark-field system's ADC module are given in Figure 3. As the figure shows, several different classifiers have been built for this tool with accuracy and purity results typically exceeding 80%. Achieving such results was more challenging in a few other cases, specifically for an intermetal dielectric classifier, which could not be resolved to acceptable levels.

Figure 3: Examples of accuracy and purity measurements of classifiers built for a dark-field inspection system: (a) classifiers used to monitor poly deposition, and (b) classifiers used to monitor tungsten CMP.

The classifiers that have been released for production-line use have proven to be portable between different devices having the same technology. Measurements that demonstrate this portability are shown in Figure 4. In this example, the classifiers were built to monitor the tungsten CMP process used for a particular device, labeled device A in the figure caption. When a new device (labeled device B) was brought on, the same classifier set required virtually no changes to work within similar accuracy and purity levels, as shown in Figure 4b.

Figure 4: Accuracy and purity measurements that demonstrate tungsten CMP classifier portability between two devices within the same technology group: (a) data for device A and (b) data for device B.

The fab uses PCM methodology to monitor DUV lithography process tools. The schematic in Figure 5 illustrates the basic process flow for the photocell monitor. This is a standard flow, except that it starts with a bare pilot wafer. All of the wafers examined by the PCM system are recycled, which minimizes the costs associated with this inspection step. The table in Figure 5 plots an example of ADC and manual classification results, while also showing yield-limiting satellite and E² nozzle defects that were detected. These defects may create either small or missing contacts at the contact and via levels on product wafers. In this example, the onboard ADC module classified both yield-limiting defect types with better than 95% accuracy and purity. The classifiers used with this tool have proven stable for several months, requiring only minor touch-ups.

Figure 5: The basic process flow of the PCM method used to monitor DUV lithography tools (at left) and an example of the PCM tool's onboard ADC results plotted against manual classification results, along with micrographs of the yield-limiting defects.

Figure 6 includes a composite wafer map of 42 different wafers run on the PCM when the two types of defects mentioned above were detected. The signature of the satellite defects is evident in the outer ring of the map, while the E² nozzle defects exhibit a distinctive signature of two radial streaks, 180° apart. The number of satellite defects was reduced considerably following the inclusion of a prerinse delay of several seconds on the developer, and the E² nozzle defects were eliminated by implementing a faster puddle-building spin speed. After these process changes had been made, the defect density on the SPC charts dropped significantly, as seen on the chart in Figure 6.

Figure 6: Composite wafer map of 42 different wafers run on the PCM and the signatures of the satellite and E2 nozzle defects (at left), and an SPC chart for the process after changes had been made to correct these problems (at right).

One unusual signature on the wafer maps became apparent only when the yield information management system's analysis module was used to perform a wafer-map gallery review. The results of this exercise prompted a further review of the ADC results, which pointed to a particular developer as a source of E² nozzle defects. It was then determined that this tool had a carbon dioxide problem. The developer was shut down for two days until the problem was resolved, which eliminated the potential for defect excursions that could affect device yields. This experience convinced the lithography engineers of the importance of performing regular wafer-map gallery reviews in addition to using a photocell monitor.

Based on the results of this investigation, the DMOS 5 fab has concluded that the benefits of on-line ADC include a lower cost of ownership and faster time to results. However, challenges still remain for both the fab and the equipment supplier. First, maintaining the desired accuracy and purity level of at least 80% requires that the fab commit engineering resources to accomplish this task. It can be a full-time job to monitor the ADC results in production and then tweak or build new classifiers as necessary. Moving more ADC classifiers into production use also requires that the fab assign additional resources to the project. Finally, some of the classifiers built for the dark-field inspection tools' ADC modules never yielded production-worthy results because of the difficulty of redetecting defects originally revealed by the dark-field tool with a bright-field ADC system. The tool supplier is pursuing software improvements that will address this issue.

Results, Benefits, and Challenges of the Data Analysis Module

The DMOS 5 fab typically uses recipes from the yield information management system's data analysis module for automating repetitive analysis tasks. The software's object-based graphical user interface allows the user to drag and drop the various simple analysis elements and connect them to form recipes. Once the recipes are built, a scheduler is available to trigger a particular recipe by either time or event. The analysis results can be in a variety of formats, including graphs, text-based summary files (with delimiter options), wafer-map galleries, and image galleries. Thus far, the fab has used the software's trend chart capabilities for tool-matching activities and to identify out-of-control situations. In the future, it plans to also use the data analysis module's yield-modeling features.

Figure 7 demonstrates the analysis module's ability to perform a loop comparison of the tungsten etch and tungsten CMP process steps. The analysis recipe, built by a fab engineer, was constructed by using a browser to interface to the database and then selecting which lots, devices, technologies, or combination of these sample types to include. In this recipe, the loop is separated into the tungsten CMP and tungsten etch process steps and the relevant ADC results are used to generate an SPC chart for each process. The SPC charts are set up to trigger actions whenever control limits are exceeded. A warning message can be shown on the screen to indicate an out-of-control situation, and the system can also be programmed to send e-mail to various responsible parties or to notify a pager via the e-mail system.

Figure 7: Output screens for a loop comparison of tungsten etch and tungsten CMP processes, which illustrate how the fab uses the analysis module to build and execute repetitive analysis tasks.

Another example in which the use of the analysis module has been helpful occurred during a defect source analysis exercise. The established method of using the optical review station's methodology for sampling defects from a wafer map was found to be oversampling the areas with high defect density. When a die-based sampling strategy from the analysis module was substituted, more-uniform defect samples resulted, as shown in Figure 8. Although the new sampling strategy includes 100% of defects from adders, it limits the number of defects selected per die and sets a percentage for defects selected from clusters. As a result of using the more-uniform defect samples for review, more-representative defect densities by defect type have been observed on both wafer-to-wafer and lot-to-lot bases.

Figure 8: Comparison of an original wafer map, a sample generated by an optical review station, and a sample generated by the analysis module.

The fab's use of the analysis module has also led to improvements in data extraction speed, which results in faster lot disposition and earlier containment of yield-limiting defect excursion events. In addition, the automation of repetitive analysis tasks allows engineers to focus on solving yield problems rather than searching for data.

The challenges still to be met in optimizing use of the module at the DMOS 5 fab include improvements to the system's interface with the fab's MES and to the versatility of automated Web reporting. In addition, spatial signature analysis must be integrated within the module, along with the utilities and capabilities of some of the supplier's other data-handling tools, specifically KLA 2552 and Quest. A final challenge is to have a presentation gallery available to build standard format presentation-quality reports that incorporate wafer maps, charts, and images on a single page. All of the issues are being addressed by the supplier, which expects to incorporate some of the desired improvements in the software version scheduled for release in the summer of 2000. Other features will be covered in software customized for the fab.

Payback Analysis

Return on investment, or payback, analysis was the lever used to convince the fab's management to purchase the analysis module after a software evaluation had been performed. A large payback in a short period of time was needed to justify the system's cost.

This analysis began by comparing the capabilities of the fab's internally developed data management system with those of the analysis module. A time study was used to evaluate how rapidly the two systems carried out the operations commonly performed in the daily routine of lot disposition. These operations included the basic functions of managing wafer maps, looking at images, and evaluating the work-in-progress (WIP) history to determine any tool or process commonalities that might explain an excursion event.

Figure 9 shows the results of the time study. The analysis module provided definite time savings in the areas of wafer-map and image viewing. Although it had no impact on the time required to evaluate WIP history, the next version of the software is expected to produce time savings there as well, as a result of integrating the updated module with the fab's MES WIP system. For troubleshooting single-lot events, the time savings provided by the module totaled a few hours a day, while excursion events involving multiple lots provided significantly more time savings. The saved time can be applied to reducing the queue of lots requiring analysis or toward yield improvement activities.

Figure 9: Results of a time study comparing the capabilities of the fab's internal data management system (DMS) and the analysis module in troubleshooting defect excursion events.

These time-study results, which represent the time saved per defect excursion event, were then used in a model to predict the fab's overall return on investment. This exercise entailed using fab-specific numbers in a series of equations (detailed in the accompanying box), which calculated the net value of the analysis module on a per-month basis. The data used in these equations include the number of affected wafers per event, the evaluation time spent per wafer in manual mode minus the time spent per wafer in automatic mode, the number of lots running at the fab per minute, the average selling price of the device, the number of wafers in a lot, the number of lots saved per day, and the yield impact per day or month of excursion containment.

One rule of thumb used in the industry is that two engineers working 100% on yield issues equates to a 1% yield increase during ramp. By supporting routine data extraction, the analysis module allows more engineering resources to be devoted to yield improvement activities, which should lead to yield increases that can be estimated and applied to the payback analysis calculations. The overall return on investment is calculated using the combination of wafer disposition and yield-learning values over time, until the break-even point is attained. In this case, hardware purchase costs also had to be included in the calculations because a new server was needed to support the quantity of data generated by connecting all defect inspection and review tools to the new yield information management system.

Conclusion

The implementation of on-line ADC and an automated data analysis module at the DMOS 5 fab has confirmed that these systems can be powerful tools for yield improvement. The addition of ADC to on-line dark-field, bright-field, and photocell monitor inspection tools was shown to add value by reducing the need for manual review and by ensuring data consistency. The analysis module adds value by enabling quick response times, by automating repetitive analysis functions, and by providing more-uniform review samples. Both the fab and the equipment supplier are addressing the challenges that remain, which should lead to additional benefits in both the near and long terms.

Acknowledgments

This article is based on a paper originally given in October 1999 at the Semicon/Southwest Yield Management Seminar. The authors would like to acknowledge the valuable contributions of Hau Do, James Hallowell, Roger Lancaster, and Brian Vialpando of Texas Instruments; Dale Sheu of Sematech; and Raleigh Estrada, Chris Lee, Ingrid Peterson, Stuart Riley, Mike Rodriguez, and Mike Taddi of KLA-Tencor.

Frank D. Poag is a member of the yield enhancement team at Texas Instruments's DMOS 5 fab in Dallas and a member of the company's technical staff. He joined TI in 1978 and has held a variety of equipment engineering positions over the years. Poag has coauthored several papers and holds a number of patents related to defect reduction and equipment improvements. A registered professional engineer in the state of Texas, he received a BS and an MS in electrical engineering from the University of Houston. (Poag can be reached at 972/927-7944 or f-poag@ti.com.)

Doug Paradis is the yield enhancement manager at Texas Instruments's DMOS 5 wafer fab. He joined TI in 1978 after having spent two years at General Electric. Paradis has held various positions in CMOS product and process integration, focusing during the past several years on yield enhancement and the improvement of in-line defect detection methodologies. He received a BSEE and an MSEE from the University of South Carolina in Columbia. (Paradis can be reached at 972/927-4942 or dparadis@ti.com.)

Mahesh Reddy is a senior applications engineer for KLA-Tencor in Dallas, directing TI's in-line monitoring use of defect inspection tools. Since 1997 he has been working in yield enhancement activities and ADC technology implementation for KLA-Tencor at Texas Instruments's DMOS 5 and K-Fab facilities. He received a BS and an MS in electrical and computer engineering from Carnegie Mellon University in Pittsburgh. (Reddy can be reached at 972/664-8320 or mahesh.reddy@kla-tencor.com.)

Jon Button is a senior applications engineer at KLA-Tencor for wafer inspection and analysis tools. Since 1997 he has been involved in the field introduction and implementation of the Model 2138 bright-field microinspection systems and the Klarity database module at Texas Instruments. He received an AS in electronics from DeVry Institute of Technology (Kansas City, MO) in 1987. (Button can be reached at 972/664-8346 or jon.button@kla-tencor.com.)

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