Meeting continues industry's drive to chip in on economic model

For such a small piece of real estate it carries a lot of weight. Its tyrannical demands will have engineers and executives meeting once again during the annual Semicon West trade show. International Sematech will host the fifth in a series of meetings to discuss how to continue building on this minuscule plot for the least amount of money. We're speaking, of course, about a square centimeter of silicon. At a global economic symposium on July 14 the consortium will present the latest update on its efforts to model the dynamics of the relationship among chipmakers, their suppliers, and the microchip. Planners hope to further a dialog that will lead to agreement on an effective way to reach the technology milestones in the International Technology Roadmap for Semiconductors (ITRS) without running out of gas.

Is it safe to say then that technology has taken a backseat to the dollar in the semiconductor industry? "Technology has never really been in the driver's seat," responds Randy Goodall, the chairman of the conference and associate director of the manufacturing methods and productivity division at International Sematech. "It always looks that way, but nobody goes to the next technology node because their techie guys want to do something marvelous. It's always been about dollars per square centimeter."

Ultimately, adds Goodall, "it's all economics." As one of the founding members of I300I, he knows that the transition to the larger wafer size and "all of the productivity enhancements that we do . . . are all done to drive down the cost per square centimeter of silicon."

How do you lower that cost and adhere to Moore's Law without unduly burdening either chipmakers or suppliers? That's the question this group grapples with. "There's never been an industry that is so . . . in need of technology revolution on an ongoing basis to the point where it's the business focus. That's where the semiconductor industry is unique," Goodall points out. "It's imperative to have this huge focus on the technical community to endeavor to come up with these regular sorts of miracles."

Miracles may arrive regularly; however, so do unholy business downturns. The entire industry economic modeling project arose in response to a combination of the two factors in the bad old days of two years ago, Goodall relates. The origins lay in the "I300I era of International Sematech, where we were in the serious stuck-in-the-mud mode of late 1998." Sematech met with suppliers to discuss "bootstrapping the industry when the industry was suffering and didn't have enough money to do R&D, and we were asking them for more tools, faster, with new technology and larger wafer sizes."

That meeting led to four others, the most recent in April. He calls that spring confab "the best meeting yet." Project leaders shared a first draft of the economic model, which combines "bottoms-up chip-level demand and top-down computations," says Goodall. The group "actually overlaid some industry revenue scenarios" on top of these calculations "and blended all those things to see what might happen to supplier revenues." The group also examined 300-mm scenarios as well as the "classical three-year technology nodes and two-year technology nodes."

Project coordinators are striving mightily to make the model as objective as they can, Goodall emphasizes. One of the revenue scenarios factors in "an overcapacity downturn in 2003 . . . overlaid onto a bottoms-up model look at the impact on suppliers." Of the participants at the April meeting the conference chairman says: "I think they felt we were trying to have an unbiased look at scenarios that could occur based on past history. It wasn't an 'all-good-news-or-pressure-suppliers-to-do-all-that-we-say' message."

"The thrust in the last few meetings has been to try to do a very thorough check that the economic model is looking at the parameters that do indeed drive the market," says John Cossins, the U.S. strategic marketing manager for ASM Lithography (ASML) and participant at the spring meeting.

At the April conference Cossins gave a presentation that proposed a framework for a lithography supplier return-on-investment (ROI) module. Cowritten by John Wiesner, a senior vice president of engineering at Nikon Precision, the presentation showed the pressures facing suppliers caught in what Cossins terms "the vicious cycle we go through in these industries."

"One of the strongest points we wanted to put across at ASML is that the industry recovered at exactly the same time as people were considering the transition from steppers to scanners," he emphasizes. The supplier was whipsawed by a rapid shift from the use of the former tool to the latter. ASML found itself coping with an industry that was "80% steppers and 20% scanners and then the following year went to 80% scanners and 20% steppers within, say, 5%.

"If this had happened at a different time in the business cycle the transition would have been smoother," Cossins laments. Instead of seeing a year in which a gradual 50-50 transition eased the supplier's burden, ASML had to deal with severe parts shortages that made the need for industrywide planning all the more apparent. The ASML presentation noted that the rapid introduction of new technology threatens productivity and yield and carries with it the risk of higher process development costs.

The meeting during Semicon West will have a segment on lithography, which is "always singled out because it's a technology-driving aspect of the industry," notes Goodall. He says the industry is at the point of "moving away from historical optical extensions to some degree." A lot of R&D dollars "are stacking up right around now" as the industry examines alternatives such as extreme UV and Scalpel, says the conference chairman.

Getting a handle on developmental costs isn't going to be easy, though. "If you've got three competing technologies dividing the market by thirds," problems are magnified by a factor of 10, since each of the technologies "is going to get a third of the market," Goodall points out. "We're trying to create a model of what the chip-level demand might be, what the integrated device manufacturers' response to chip demand might be, and then [factor in] some scenarios from the 200- to 300-mm transition and . . . the technologies from 0.18 to 0.13 to 0.10 µm." Sema-tech wants "to engage the suppliers themselves and ask, 'What does it cost to do one of these generations? Can you spread out R&D for all aspects of 200- and 300-mm, and can we group them all together for R&D purposes for 193-nm lithography?' "

The Sematech team has made some efforts to link the economic model to yield benefits, says Denis Fandel, a Sematech productivity analyst who works with "advisory folks from Intel and IBM as well as suppliers." Yield-learning curves are built into the model "to try to at least emulate what's going on from an overall industry point of view. As such, we tend to be very sensitive to those particular aspects of manufacturing. Because we tend to be really manufacturing oriented we certainly try to deal with those things, so it's an important ingredient in our model. It certainly has a dramatic effect on the results, depending on what type of learning curves you assume."

Goodall adds: "It's not beyond the realm of possibility to look at yield maps as factories come on line and do sensitivity analyses on how fast those curves move to the number of fabs that really need to be built." With chipmakers building "dozens and dozens" of multibillion-dollar fabs annually, "they need to get their yields ramped up quickly."

In April the participants began to consider the effect of using foundries on the industry's economic model. It's a topic that Sematech also planned to address in a meeting in early June. "In the model we presented in April we did not have a separate IC construct for foundries. We're actually wrestling with that right now," Goodall says. He points out there are "some pretty polar arguments" on whether foundries accentuate or dampen industry cyclicality. One line of reasoning holds that foundry use "minimizes the overcapacity situation . . . and might eventually damp out some of the historical oscillation." However, "the fact that 20 IC companies all want 15 to 20% of the market is a problem we continue to live with."

On the other hand, competitive pressures usually dictate that integrated device manufacturers (IDMs) "will not farm out their critical products to foundries," Goodall notes. Once a downturn begins, the IDMs "pull back on the foundries," giving them their less competitive products. "The foundries who are spending most of the money in capitalization plans suddenly put the brakes on the largest building segment and this really throws the suppliers through a loop." Needless to say, this line of reasoning holds that using foundries worsens the business cycle.

Sorting out all these factors and putting them into a workable model will take an ongoing effort, Fandel says. He envisions a point in the future where the work "will stabilize enough so that we're able to reduce the amount of effort and energy we're putting into it." He doesn't see that happening in the near term, however. He says Sematech plans to ask some universities to help incorporate some of the macroeconomic factors that have an impact on the industry. "In that way we hope to broaden our basis for this work and create more of a lasting set of models."

"This activity is at a fairly technical level in terms of economic issues," emphasizes Goodall. "It's intended to feed this higher-level industry executive forum process where executives from IC companies and equipment suppliers can talk about these big problems in an industry that doesn't have quick and easy answers."

Despite some uncertainty about the ultimate product, Cossins likes the fact that the Sematech-led effort has created a forum for sharing information. "Reasonably, it's very difficult to quantify what's going to come out of the meetings. The biggest achievement is bringing together semiconductor manufacturers and equipment suppliers in the same room to talk about the effect of technology acceleration and gain a mutual understanding of the concerns on both sides." He says the ITRS "was developed by semiconductor manufacturers with relatively little discourse with the equipment suppliers."

Ironically, the need for a workable economic model became evident at the April meeting, which, Cossins says, "was more or less overtaken by pure delivery considerations for lithography equipment. The original brief of the industry economic forum meeting was to come up with a validation for the technology roadmap, to see what effect the map has on the industry. But because of the current upturn in the industry it more or less turned into a 'when-the-hell-can-we-deliver-one-of-these-type-things' meeting."

By no means, though, is the ASML official discounting the positive aspects of the overall effort. Cossins recalls being pleasantly surprised when one of the semiconductor manufacturers at the April session suggested the company might be willing to offset some of the costs involved with stockpiling hardware. The offer came during a discussion about the long lead times required to develop lithography systems. "There's a fear of ordering deep UV today because it takes a year to a year and a half to build inventory. Then the industry goes through a downturn and we're left with all this inventory.

"The company in question suggested it might be ready to absorb some of the financial risk," marvels Cossins. "That was a first."

The International Sematech global economic symposium will be held at the Palace Hotel, San Francisco on July 14. Information: 415/512-111; fax, 415/543-0671; http://www.sematech.org.