Building Copperopolis II

Developing a defect reduction strategy for the copper dual-damascene oxide etch process

Peter Biolsi, IBM Microelectronics; and Steve Ellinger and Daniel Morvay, Lam Research

In a new defect reduction strategy, patterned wafers replace bare silicon wafers to perform line monitoring and detect particles responsible for yield loss on copper production wafers.

Particles and the defects they cause have long been a problem in semiconductor manufacturing. Since the first cleanroom was built, particle detection and reduction have been major concerns in the industry. Particle sources may be classified into three categories: particles from the fab atmosphere, particles caused by the handling of wafers, and particles generated by manufacturing tools and actual processes. Improvements in cleanroom design have greatly reduced airborne particles, and advances in cleanroom procedures and wafer-handling techniques have resulted in fewer particle sources.¹ But particle generation caused by wafer fabrication tools and their related processes remains a challenge.

Single- or dual-damascene processes using copper, the most important future metallization techniques for creating interconnects, are very sensitive to particles.² Particles deposited on a wafer during copper processing may cause opens from blocked etch, problems with via etch process steps, or shorts as a result of scratches caused during chemical-mechanical polishing (CMP), an integral but dirty step in copper processing.³

Defect sources can be classified into four categories: particulate, metallic, organic, and other types.⁴ Particles deposited on the wafer can cause local roughness that may later cause problems in the photolithography step. Particles can also lead to the formation of pinholes in films deposited later. Because metallic contamination can lower an IC's breakdown voltage, copper contamination will become a growing concern on the process line as its use increases. Organic contamination is the least-studied source of defects, while scratches and dielectric film stress are common process-related problems.³

As geometries shrink, microelectronic fabrication processes become more complex, forcing semiconductor engineers to develop strategies for reducing particle-based defects. An example of this complexity is contact etch, in which the etch rate decreases with a decreasing hole diameter.⁵ This situation requires longer etch times to completely etch through a dielectric layer. Contact hole sizes range from 0.1 to 1.0 µm, dictating acceptable particle specifications.⁶ For example, while a 0.1-µm particle will block a hole that is 0.1 µm in size, it will not block one that is 1.0 µm in size.

Because of the increasing demands of particle specifications, end-of-line process and tool requirements are becoming increasingly stringent in the semiconductor industry. The tight geometries found in small feature sizes contribute to the faster chips the market demands, but these geometries must also demonstrate improved performance based on decreasing defect densities. Yesterday's acceptable defect densities are today's killer defects. Facing this challenge, IBM Microelectronics's facility in Burlington, VT, completed a successful defect reduction program on the 4520XLE oxide etch system from Lam (Fremont, CA), which is used for copper dual-damascene processing. Defects were identified using in-line metrology. The defect reduction program successfully identified problem components, redesigned those components, and tracked improvements in defect levels through both in-line metrology and yield controls. At the successful completion of the project, a significant increase in mean-time-between-clean (MTBC) was demonstrated, with no degradation of line performance.

This article discusses the methodology that was used to determine the source of the defects, correct hardware problems that were a source of particles, and verify that defect levels had in fact been reduced as a result of installing new hardware. The article also explains how a short-loop monitoring system using monitor wafers to determine particle levels helped to quantify particles on the etchers under investigation and compared these etchers to the rest of the manufacturing line. A statistical approach that helped to reduce the variability of the line controls is also presented. This approach ultimately led to the MTBC increase while keeping yields constant.

Identifying Yield Loss and Defects

It has been estimated that up to 80% of the yield loss in a mature, high-volume fab is a result of random particle and pattern defects.⁷ This has prompted yield engineers to create in-house yield management systems that track defect data. These systems typically involve data collection from process tools with in-line defect and electrical-test inspection points, data storage, and data analysis.⁸ Teamwork between the fab and the toolmaker is also essential for reducing defect levels and improving yields.

The process of reducing defects at the Burlington facility began with the yield engineers, who identified a significant yield loss that originated in the trough and via etches of semiconductor devices. Blocked fill, causing opens in the metal lines, along with blocked etch were the yield loss signatures and were traced back to single- and dual-damascene process steps. Functional yield, when plotted against etch radio-frequency (RF) minutes, began to degrade after 4000 RF minutes on any given oxide etch chamber. However, based on in-line measurements, the wet clean target of 12,000 RF minutes did not appear to be affected. (To protect yields, the wet clean limit was set to this intentionally low threshold, which was greatly below expectation.)

The blocked etch and fill appeared to be particle related, but traditional particle testing did not indicate any problems. The traditional particle test involves starting with a clean, bare silicon wafer, scanning it for particles, running the wafer through the etcher using a gases-only recipe, and scanning the wafer a second time for particles. Subtracting the particle results of the first scan from those of the second determines the etcher's particle contribution. With a fail limit of 50 adders or more, the particle level easily remained within specifications up to the wet clean limit of 12,000 RF minutes.

Figure 1 shows no samples that were above the limit of 50 particle adders. Most samples were well within the specification limit, and distributions appeared random throughout the wet clean cycles of 12,000 RF minutes. Successive wet clean cycles failed to show any recurring trends or problems. While the test reflected in Figure 1 was being performed, the patterned-wafer defect inspection tool was collecting defect information on product wafers that were undergoing pre- and postetch inspection. Using defect maps from the pre-etch steps, particles were subtracted using the x-y coordinates of previously discovered particles from prior manufacturing steps. Since this technique was new to the fab, the final subtracted value was then plotted on a chart and monitored. Because data had not been collected over time, pass or fail criteria had yet to be established.

Figure 1: Plot of particle counts on bare silicon wafers and RF minutes. (The thick line indicates the inspection limit.)

Figure 2 shows patterned-wafer defects plotted with RF minutes. This chart indicates that after a wet clean, patterned-wafer defects generally were low. As RF minutes increased, the defect counts generally, but not consistently, increased. This trend appeared to be replicated over multiple etchers and multiple wet clean cycles. It was unclear why particle counts sometimes increased dramatically after a wet clean and at other times remained low. Initial investigations into the fliers (very high particle counts) seen in Figure 2 attempted to correlate the patterned-wafer defects with bare silicon defects. However, the bare silicon wafers that were run in an attempt to partition the etcher were consistently below the fail limit. Moreover, data plotted to find trends between patterned-wafer and bare-wafer defects indicated that there was no correlation.

Figure 2: Plot of wafer defects on patterned product wafers and RF minutes. (The thick line indicates the inspection limit.)

Figure 3, which plots bare silicon particle adders against patterned-wafer particle adders, indicates that the occurrence of high levels of bare silicon particles did not mean that there would be high levels of patterned-wafer particles. Because the bare silicon wafers were processed using gases only in the main chamber process, the difference between the particle adders on the bare silicon wafers and those on the patterned wafers was attributed to a lack of RF in the bare silicon particle recipe. Since the yield data agreed more closely with the patterned-wafer adders than with the bare silicon adders, it was deduced that defect counts were more sensitive on patterned wafers. It was therefore necessary to confirm the validity of the patterned-wafer data and determine whether a better particle monitor was needed to partition the etcher.

Figure 3: Plot of particle adders on bare silicon wafers versus particle adders on patterned wafers.

Validating the Defects

Both optical and scanning electron microscopes (SEMs) were used to determine if the particles detected, after excluding prior-level defects, were on the surface or in the dielectric film. Surface defects clearly indicated that particles were added during etching or handling. Film particles definitely were not caused by the etcher or the etch process. False counts were periodically found, but they were more the exception than the rule.

To alleviate the burden on the manufacturing process, a sampling inspection plan based on an inspection limit for certain product types was established instead of 100% lot inspections. No optical work was performed on samples below the limit, while for those above the limit optical pictures and some SEM images were taken as time allowed. All pictures and maps were posted on a server for examination. These pictures showed that the defects were real and that most were on the wafer surface. Some of the optical and SEM images that show defects are presented in Figure 4.

As the optical images indicate, most defects were translucent while some were opaque. Energy-dispersive x-ray or other chemical analyses were not performed on these samples but had been performed on similar samples found at other times, resulting in the discovery of silicon dioxide, fluorine, and aluminum fluoride particles. The radio frequencies of those particles were similar to those of most of the particles found in the study discussed here, which are shown in Figure 2. Because the bare silicon particle tests did not indicate any contamination or trends, it was decided that a more-accurate particle monitor was needed to qualify production.

Creating a Short-Loop Monitor

Daily meetings were begun to review the defect data obtained from the previous 24 hours and to implement a particle qualification procedure. A review of the defect maps and the optical pictures indicated that real defects were randomly scattered on the wafer. However, no single type of defect predominated. The defects were angular, mostly transparent, and on the top. The wet clean frequency had already been fully implemented to 4000 RF minutes, but random defects continued to be generated by the etchers. Nevertheless, in-line yield doubled during this time and functional yield quadrupled.

Because it was still necessary to track down the source of the particles in the etch process, a "short-loop" monitor was created to qualify the etch chambers and to enable the partitioning of the etchers. This monitor uses the same photo pattern as that used in the damascene etch process and is able to simulate the etch process completely. A thick dielectric film is applied on a clean wafer, the damascene photo pattern is placed on top, and the wafer is etched as if it were a product wafer. All of the normal manufacturing steps are used for the etch process because the historical defect data indicated that defects were found on the product wafers but not on the bare silicon monitor wafers.

New defect detection recipes for patterned-wafer inspection at both pre- and postetch steps were created so that partition experiments could begin. The short-loop monitor closely tracked production defects and had no prior-level problems that could obscure the results. This monitoring procedure not only pointed to the main etch chamber as the source of the particles but also allowed the manufacturing line to qualify production after a wet clean or other chamber-open event. Later in the defect reduction program, the short-loop monitor indicated that the production wafer-defect detection recipes were counting the prior defects as deposited on the wafer surface.

The Etch Chamber: The Root Source of Particles

Chemical analyses performed on particles found on wafer surfaces indicated the presence of silicon dioxide, fluorine, and aluminum fluoride. These analyses were performed by paying close attention to the patterned-wafer scans from both product wafers and the short-loop monitors. Since wet cleans seemed to generate some of the higher defect counts (and premature wet cleans had occasionally been performed to solve unrelated problems), the etch chambers were examined during wet cleans. Determining the locations of polymer buildup was especially important and useful for diagnosing particle traps and generators.

Figure 4: Matching optical and SEM images of defects found on patterned wafers.

Figure 5 represents the Pareto of particles and their locations in the chamber after successive wet strips had been performed on multiple etchers. Electrode particles represented the highest category and were found at every wet strip in varying concentrations. These particles, which were found between the gas distribution aluminum baffle and the upper electrode, were powdery and accumulated with increasing RF minutes. The sputtering of the aluminum baffle from the plasma and the aluminum's reaction with the process chemistry to create aluminum fluoride was the source of the powder and the electrode hole pattern etched in the baffle. A chemical analysis of the particles indicated the presence of aluminum fluoride, which confirmed the sputtering theory. Figure 6 depicts the assembled electrode and Figure 7 the aluminum baffle sputtering. Figure 8 shows the backside of the electrode, the right half of which had been wiped with a cloth that had been dipped in isopropyl alcohol.

Figure 5: Pareto of particle occurrences and hardware locations.

Figure 6: Assembled electrode.

Figure 7: Aluminum baffle sputtering.

Figure 8: Backside of the electrode, the right side of which had been wiped with a cloth dipped in isopropyl alcohol.

The next item in the Pareto presented in Figure 5 was gate-valve particles. Instead of being a recurring problem, these particles appeared to be eliminated through a single clean of the gate-valve slide area. Successive wet strips showed that the gate valve remained clean and may simply have been subjected to particle buildup over a lengthy period of time. While these particles were not analyzed, it was thought that they were composed of aluminum fluoride mixed with process residues.

Pump ring cracks, the next item reflected in the Pareto shown in Figure 5, appeared not as a particle generator but rather a particle trap. The pump ring, which is composed of ceramic material, had random chips on its outer diameter. Further investigation showed that the size of the ring's outer portion was almost equal to that of the inner diameter of the chamber. Because the ring's tolerances were very tight, which caused it to jam at a slight angle in the chamber during installation or removal, it had to be loosened with a rubber mallet more than once.

The next item in the Pareto in Figure 5, melted nylon screws, had been damaged by unconfined plasma. Because the tuning cap and gate-valve positions had not undergone recipe optimization, hardware controls were delayed, allowing the plasma to couple to the chamber wall. This problem heated the outer portion of the confinement rings and melted the screws, causing the formation of particle traps as well as particles. Figure 9 illustrates the damage these screws sustained.

Figure 9: Screws that had been melted by unconfined plasma.

The last item in the Pareto in Figure 5 was chipped quartz from the edges and screw holes of the quartz confinement rings. During chamber operation, the plasma reactants chemically attacked the quartz around the screws, making it brittle. The brittle quartz then chipped as the screws were inserted or removed during chamber maintenance. An example of the chipping around the screw holes is presented in Figure 10. During installation, scraping against the outer edges of the rings and the sharp edges of the quartz surrounding the screw holes also caused these edges to chip and crack. The photograph of the rings in Figure 11 shows the outer edges and the thick quartz.

Figure 10: Chipped quartz in the screw holes.

Figure 11: Quartz confinement rings with chipped edges.

Solving the Materials Problems

The hardware engineering group at Lam examined and redesigned the etcher components to minimize or eliminate hardware-related particle generation. To minimize the effects of aluminum fluoride caused by aluminum baffle sputtering, a baffle replacement made of silicon carbide was created. Limited customer data indicated an improvement in the particle performance as a result of this change. Although baffle sputtering was not eliminated, its by-products—silicon and carbon—react with the process chemistry and volatilize because of the new baffle. Gate-valve particles, after the initial clean, did not recur. Therefore, no further action was taken.

Reducing the outer diameter of the ceramic pump ring at the top and bottom eliminated the chipping that had resulted because the ring was too large. The pump ring can now be installed at up to a 30° angle without binding. Figure 12 is a photograph of the new pump ring.

Figure 12: New pump ring.

The melted nylon screws were replaced with new, tougher polymer screws. Polymer is stronger than nylon and has a higher melting temperature. Ultimately, it was found that optimizing the recipe set points of the gate valve and the tuning caps increased the confinement of the plasma.

Finally, the chipped quartz rings were redesigned with radiused corners, preventing the sharp edges from scraping against each other. However, it was found that with increasing use the quartz rings become thin and prone to chipping, requiring that they be replaced at regular intervals.

Solution Confirmation

After the components were redesigned, four hardware sets were shipped to the field for testing. After one of the sets was installed, no adverse defect or process effects occurred on the product wafers. However, the hardware did not cause the expected reduction in defect counts, although the high fliers were not as high as they had been historically and their distribution was beginning to settle at lower averages. Figure 13, which shows patterned-wafer defects over time, indicates that while defects did not decrease immediately after the hardware installation, their distribution gradually tightened and defect levels eventually fell below the inspection limit.

Figure 13: Patterned-wafer defects before and after the new hardware installation.

Defect levels were thought to decrease slowly because of the presence of residual aluminum fluoride concentrations in the etch chamber. Although the wet clean procedure produced a very clean chamber, it was believed that some quantity of this nonvolatile compound had not been removed during cleaning because it was present at relatively inaccessible locations.

The remaining three hardware sets were installed to evaluate their ability to replicate the results of the first set and to study process interactions. Of the four etchers under evaluation, one of them performed integrated etch and resist strip processes, one performed the etch process only, one performed state-of-the-art processes, and one performed all processes.

The data in Table I, which were compiled after the new hardware had been installed and the evaluation period was completed, indicate that the etcher with the integrated etch and resist strip processes generated the fewest number of particles. This table also shows that every etcher under evaluation generated fewer particles than etchers that had not undergone the hardware retrofit. While this particle reduction did not occur immediately upon installation, over time the number of particles decreased and were maintained at those lower levels.

To test the reliability of the new hardware, the etchers under evaluation were run until particle failure occurred or for 30,000 RF minutes, whichever came first. Particle levels were monitored daily as a preventive measure against possible problems. However, none were found, and the etch chambers were successfully run for 30,000 RF minutes, as demonstrated in Figure 13. This run time represented a 750% increase in the number of RF minutes between wet cleans over the run time for the system before the new hardware was installed. Final test yields for the etchers running for 30,000 RF minutes were compared to those running for 4000 RF minutes. No significant differences were found between the two populations.Verification tests of the 30,000-RF-minute limit between wet cleans were concluded after all the evaluation chambers had been run several times to this limit. Each chamber reached 30,000 RF minutes at least twice, except for the etcher performing the etch process only. Based on this test, the investigators concluded that when an etcher performs the resist strip process, this helps to condition and remove particles.

Conclusion

In order to wage a successful defect reduction campaign, the engineering groups responsible for the project described in this article—the hardware team, the vendor, the yield analysis group, and the manufacturing personnel—had to work closely with one another. Without this cooperation, the project would not have succeeded.

In this investigation, it was determined that bare silicon wafers were no longer sufficient for defect detection line monitoring, but had to be replaced with new patterned wafers to detect the particles responsible for yield loss on production wafers. Both production and short-loop monitors were used as part of the defect reduction efforts. Short-loop monitors were used for the daily qualification of the etch chambers, providing a standard and a means to check production wafer defect counts. In addition, the short-loop monitors were able to partition the etchers.

Once metrology was performed and particle levels were verified, problems linked to wet cleans performed in the oxide etch chambers became evident. Investigations performed during the clean operation revealed that the etchers' hardware had to be redesigned or replaced. While the installation of new hardware did not immediately eliminate particle problems because the chambers had previously been contaminated with aluminum fluoride, the hardware retrofit was able to help reduce contamination levels over time, bringing particle levels to record lows. As a result of the defect reduction strategy discussed in this article, the mean time between cleans increased by 750% in several chambers over multiple runs, while functional yield was rose by a factor of four over previous yield levels. Consequently, the final MTBC limit established was 3.75 times higher than the original limit.

Acknowledgments

A version of this article is scheduled for presentation at the Symposium on Contamination-Free Manufacturing (CFM) for Semiconductor Processing on July 10, 2000, held in conjunction with Semicon West 2000 in San Francisco. Used with permission.

The authors would like to thank the IBM maintenance and manufacturing groups as well as the Lam service group for their work on the project described in this article. In addition, they wish to acknowledge the contributions of Craig Benson, Rich Lebel, Matt Moon, Curtis Pollard, Brad Rand, and Matt Tiersch of IBM Microelectronics and Chris Carolin, Gary Farnsworth, Jim Laney, and Jeff Musser of Lam Research.

References

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Peter Biolsi is an engineer/scientist at IBM Microelectronics division in Essex Junction, VT, where he is responsible for advanced line integration. With 14 years of experience in microelectronics manufacturing as a process technician and engineer, he has concentrated on the fields of photo, CMP, metallization, and etch at IBM's research and manufacturing engineering divisions. Biolsi has published in semiconductor journals and has one U.S. patent pending. He received a BS in mathematics from Trinity College in Burlington, VT. (Biolsi can be reached at 802/878-5386 or pbiolsi@us.ibm.com.)

Steve Ellinger is a senior field service engineer at Lam Research (Williston, VT), where he focuses on advanced oxide etch processes. He has been with the company for 10 years. Previously, he was a field service engineer at Plasma Therm, where he concentrated on plasma etch and CVD systems. Ellinger has published in semiconductor journals and holds one U.S. patent. He received an AA in electronics technology from Vermont Technical College in Randolph Center. (Ellinger can be reached at 802/288-1135 or steve.ellinger@ lamrc.com.)

Daniel Morvay is a senior field process engineer at Lam Research in Williston, VT, where he is responsible for oxide etch processes. With 12 of experience in microelectronic manufacturing, he has been involved in product engineering, plasma etch, and advanced endpoint detection. Before joining Lam Research he was with Texas Instruments in Dallas, where he spent seven years as a plasma process engineer. A member of the American Vacuum Society, he has published in semiconductor journals and presented papers at conferences. He received a BS in microelectronic engineering from the Rochester Institute of Technology in Rochester, NY. (Morvay can be reached at 802/288-1121 or dan.morvay@ lamrc.com.)

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