Extreme Silicon

Investigating optical metrology issues specific to SIMOX-SOI wafers

Michael L. Alles, Robert P. Dolan, and Maria J. Anc, Ibis Technology; and Michael A. Mendicino, Motorola

Studies show that an SOI wafer fabrication process can be optimized to prevent problems associated with the use of optical characterization tools.

In existence for more than 30 years, silicon-on-insulator (SOI) technologies have been used in analog bipolar and BiCMOS processes as well as in high-temperature and radiation-tolerant digital CMOS electronics. Recently, however, increasing demands for higher-performance microprocessors and lower-power portable devices have opened a much larger market for the technologies. The unique properties of SOI devices and circuits, which include low junction capacitance, steep subthreshold slopes, minimal body effect, and soft error immunity, make them particularly attractive to the electronics industry for mainstream CMOS applications. Leading integrated circuit manufacturers have confirmed these performance advantages, long touted by researchers, and plan to introduce high-speed microprocessors as the first major commercial applications.¹ SOI has also gained increasing prominence with each revision of the SIA Roadmap, now called the International Technology Roadmap for Semiconductors (ITRS), which has guided the quality requirements for the maturing SOI materials. Indeed, significant improvement in the quality of SOI wafers has been instrumental in enabling the introduction of commercial SOI-based CMOS integrated circuits.

Separation by implanted oxygen (SIMOX) is commonly used to manufacture low-cost SOI wafers for CMOS circuits. While SIMOX-SOI wafers are compatible with bulk silicon IC fabrication processes, some aspects of the characterization of these wafers during both wafer production and subsequent device fabrication are unique, requiring special consideration as the process technology migrates from R&D applications to manufacturing environments, where efficient metrology is essential to ensuring high yields. Measurements of SIMOX-SOI-specific parameters that affect performance or yield must be included in the characterization process. In addition, the use of optical lithography with SIMOX-SOI wafers presents challenges. Studies have shown that the presence and characteristics of an oxide layer below the silicon wafer surface affect the use of optical tools. After a brief description of the SIMOX process and the properties of the resulting wafers, this article addresses the issues related to optical metrology.

SIMOX-SOI Wafer Fabrication and Parameters

An important requirement for applying SOI technology to digital CMOS integrated circuits is the high uniformity of thin (<0.5 µm) SOI wafers known as thin-film SOI. The most mature method for manufacturing these thin SOI wafers, the SIMOX process uses a high-current (>50-mA) oxygen-ion implanter to implant 2 x 10¹⁷–2 x 10¹⁸ ions/cm^–2 on the wafer surface at energies in the range of 50–200 keV. This step is followed by a high-temperature (>1300°C) anneal in an inert ambient containing some oxygen over an extended period of several hours. The wafers produced have a high-quality thin (50–200-nm) silicon layer (where the devices are built), which is isolated from the supporting bulk silicon substrate by a relatively thin (50–400-nm) buried oxide (BOX) layer. Varying the dose and energy of the implantation and the high-temperature annealing parameters can produce different silicon and BOX layer thicknesses and affect the throughput of the oxygen implanter and annealing furnaces.

The development efforts described in this article focused on reducing the oxygen dose, thereby producing thinner BOX layers in order to reduce material costs and improve wafer quality. SIMOX processes can be categorized generally as full dose (producing an ~380-nm BOX layer), medium dose (~150-nm BOX layer), low dose (~100-nm BOX layer), and very low dose (~50-nm BOX layer). A transmission electron microscopy (TEM) image of a cross section of an SOI wafer produced by medium-dose SIMOX is shown in Figure 1.

Effective SIMOX-SOI wafer fabrication requires characterization of the properties of the underlying BOX layer and the silicon top layer, including contamination levels, defect densities, thicknesses, and uniformities. Most characterization methods used for bulk and epitaxial silicon wafers are applicable to SIMOX-SOI, while others must be modified.^2,3

Figure 1: Cross section TEM image of an SOI wafer produced by medium-dose SIMOX.

Trace-element impurity levels are measured using such techniques as total reflected x-ray fluorescence (TXRF), atomic absorption spectrometry (AAS), inductively coupled plasma mass spectrometry (ICP-MS), and secondary ion mass spectrometry (SIMS). The microroughness of the top surface of the silicon and BOX layers is characterized using atomic force microscopy (AFM). Crystalline defects (threading dislocations or stacking faults) and nonsilicon defects (sometimes referred to as HF defects) in the silicon top layer are measured using chemical decoration, followed by counting under an optical microscope. The integrity of the BOX layer may be measured using copper plating (where the wafer is treated as a large capacitor) and by the fabrication of patterned BOX capacitors. Interfacial characteristics and doping in the SOI layer can be measured with point-contact transistors (where the back of the wafer is the gate and the BOX layer is the gate insulator). Defect densities measured on current SIMOX-SOI materials are below the year-2000 requirements in the 1999 ITRS, indicating that the material quality can support advanced commercial applications.

Using Optical Metrology on SIMOX-SOI Wafers

Light-scattering techniques can be used to detect contaminants, crystal-originated particles, and other defects on SIMOX-SOI wafers. However, the presence and characteristics of the BOX layer can complicate the use of these and other optical wafer characterization methods. Imperfections in the BOX layer and interface roughness may cause errors in film-thickness measurements. Optical characterization tools also may confuse real surface defects generated during device fabrication with cosmetic imperfections below the surface. If SOI wafers are to be characterized efficiently and accurately, the models used in optical measurements may require adjustment and optical metrology tools may require calibration with nonoptical techniques.

Layer Thicknesses. The thicknesses and uniformities of the silicon top layer and the BOX layer are the most important parameters of SIMOX-SOI wafers and are typically measured by spectroscopic ellipsometry (SE). Engineers must use an appropriate optical model to fit the measurements to the BOX layer because the presence of the silicon overlayer, which exhibits strong absorption in the wavelength region used for the SE measurements (~0.28 to 0.75 µm), affects the results of this measurement. For example, in one case SE measurements on a SIMOX-SOI wafer yielded a silicon top layer thickness of ~2500 Å and a BOX layer thickness of ~150 nm, while SE measurement of the same wafer following removal of the silicon overlayer by selective chemical etch in a potassium hydroxide solution yielded a BOX layer thickness of ~160 nm. The 10-nm difference is on the order of the BOX layer thickness uniformity, and precise nondestructive measurements of the BOX thickness and uniformity are difficult to obtain.

In addition to the effects of the silicon layer, the microstructure of the BOX layer itself can affect thickness measurements because it is not an ideal SiO^₂ structure and does not have perfect interfaces. Silicon precipitates (called islands) may exist within the BOX layer, which alter its optical properties compared with the ideal SiO^₂ model. Incorporating knowledge of the BOX layer microstructure into the models used in SE, such as treating the layer as a multilayer structure with a silicon-rich layer, can increase the accuracy of the measurements. In addition, measurements of the BOX layer taken with the silicon layer removed can be used to calibrate the SE measurements made with both layers present.

Light-Scattering Defects. Although particles and other surface light-scattering defects on SIMOX-SOI wafers are measured with the optical instruments used for bulk wafers, the characteristics of the BOX layer and the BOX/silicon interfaces can limit the usable resolution of such tools. The silicon islands within the BOX layer and the microroughness of the silicon top layer (~3–10 Å) and the Si/BOX interface (~10–50 Å) scatter light and can appear as defects in optical metrology measurements.

Figure 2 shows examples of full-dose and medium-dose SIMOX-SOI materials with a relatively high density of silicon islands. The size and density of such islands are dependent on the implant conditions to the first order and the annealing conditions to the second order. As seen in Figure 2 (left), in the full-dose SIMOX material the islands have a density of ~10⁹ cm^–2 and are located mainly at the bottom of the BOX layer near the substrate interface. The 10–30-nm thickness of this interface region is small (<10%) compared with the BOX layer thickness, and the islands' location away from the device layer renders them insignificant. In contrast, the island density in the medium-dose material is comparable to or less than that in the full-dose material, but the islands tend to be located closer to the center of the BOX layer and can be as large as 25–50% of the BOX layer thickness, as seen in the SEM photo on the right in Figure 2. Depending on the implant conditions, primarily dose and energy, the density of the islands can range from >10⁸ to <10⁵ cm^–2 (below the detection limit of the TEM used for Figure 1).

Figure 2: TEM image of a full-dose SIMOX material (left) and SEM image of a medium-dose SIMOX-SOI material (right). Both materials have a high density of silicon islands in the BOX layer.

The AFM images in Figure 3 are examples of the silicon top layer and the silicon/BOX layer interface following removal of the silicon layer for two SOI wafers produced by different SIMOX annealing processes. The annealing conditions tend to determine the characteristic microroughness. The light scattering caused by the "tiles" observed in the AFM images can contribute to the haze count and appear as defects when using optical metrology.

Figure 3: AFM images of the silicon top layer of two SOI wafers (top) and the silicon/BOX layer interface of the same wafers following removal of the silicon layer by selective chemical etching (bottom). The differences in the observed characteristics are caused by different SIMOX annealing processes.

When Ibis Technology (Danvers, MA) began implementing medium-dose SIMOX, it was discovered that the resulting wafers had much poorer optical quality than full-dose SIMOX materials, as indicated by high haze counts and the inability to measure particle counts below 0.5-µm sizes. Medium-dose materials with high island densities, such as that shown in Figure 2 (right), exhibited a grainy appearance when optical metrology tools were used during inspections of bare or patterned wafers, and the noise induced by background scattering caused problems at certain lithography alignment steps.

To determine whether the dominant contributing factor to the problems was the islands or the interface roughness, an experiment was performed in which a Model 2135 inspection system from KLA-Tencor (San Jose) was used to analyze unpatterned SOI wafers produced using full-dose and various medium-dose SIMOX processes. After initial measurements were taken, a selective etch removed the wafers' silicon to eliminate top-surface roughness as a source. A second set of measurements was then taken. Finally, touch polishing removed the interface roughness on the top of the wafers' BOX layer and the wafers were measured again. The results, shown in Figure 4, suggest that the presence of silicon islands in the wafers' BOX layer has an impact on optical appearance. Roughness also seems to have some impact, because touch polishing of the BOX layer surface improved the grainy appearance somewhat. The impact of islands on wafer inspection was verified by the images in Figure 5, which were taken with the same system. These images show patterned wafers produced by two different medium-dose SIMOX processes.

Figure 4: Optical images of unpatterned SOI wafers produced using full-dose SIMOX (left column) and two different medium-dose SIMOX processes (middle and right columns). The sequence of images is: with the silicon top layer in place (top row), following removal of the silicon layer by selective chemical etch (middle row), and following subsequent touch polishing of the surface of the BOX layer (bottom row).

Figure 5: Optical images of patterned SOI wafers produced using two different medium-dose SIMOX fabrication processes. The different oxygen-ion doses used affected the wafers' island densities.

Further study of the SIMOX process conditions and the performance of optical metrology tools on the resulting SOI materials indicated that island density could be reduced dramatically by optimizing the implant dose for a given energy (or set of energies). The medium-dose SIMOX-SOI material shown in Figure 1, for example, exhibits much lower island density and a much lower haze count than the earlier medium-dose material shown in Figure 2 (right). The proper choice of doses and energies during wafer fabrication can reduce island densities to the point where they are no longer a problem for optical metrology or lithography. However, when that level is achieved, roughness at the silicon/BOX layer interface can appear as defects during the inspection of patterned wafers. In particular, certain annealing conditions produce well-defined tiles, which may be detected using defect-imaging inspection methods. Examples of such tiles are shown in the images on the right in Figure 3 and in Figure 6.

Figure 6: Optical microscope image showing the tiles that can be detected by defect-imaging tools.

The studies discussed in this article show that the choice of annealing temperatures and ambients can be optimized so as to minimize both surface and interface roughness. A comparison of the left-hand and right-hand images in Figure 3 indicates that surface roughness becomes much smaller and less distinct when a different annealing process is used. Initial results of experiments using materials with low island densities and low-tile annealing parameters indicate that the issues related to optical metrology can be greatly reduced, making SOI materials perform similarly to bulk silicon.

During this work, the haze count produced by a KLA-Tencor Surfscan 6400 provided a good metric for the optical quality of SOI materials as it related to the issues that were being addressed. Figure 7 shows such haze counts for various SIMOX-SOI materials. These results agree with those from other optical metrology and lithography tools in that the tool performed poorly on materials with high haze counts and well on materials with a low haze count.

Figure 7: Haze counts on different SIMOX-SOI materials measured by a Surfscan 6400.

In addition to the research into improvements in the material fabrication process described above, investigations using more-sophisticated particle measuring systems that allow defect classification and filtering have been performed. These studies indicate that small particles ( 0.15 µm) can be measured on SIMOX-SOI materials provided that island density is not very large. All of these metrology issues should be the focus of ongoing research from both the materials development and metrology tool perspectives.

Conclusion

As SOI technologies are adopted for the production of commercial high-performance CMOS devices, the fundamental structure and process-specific features of SIMOX-SOI wafers present new metrology issues, particularly when optical measurement techniques are used. Characteristics of the wafers' buried oxide layer can affect the performance of the optical metrology and lithography tools commonly used on bulk and epitaxial wafers. Understanding the interactions between the materials and the metrology tools can enable the development of optimized wafer fabrication methods that can reduce the sensitivity of the optical tools and permit the electronics industry to take advantage of SOI wafers' unique characteristics.

References

1. R DeJule, "SOI Comes of Age," Semiconductor International 22, no. 13 (1999): 67–74.
2. JP Colinge, Silicon-on-Insulator Technology: Materials to VLSI (Dordrecht, The Netherlands: Kluwer Academic Publishers, 1991).
3. S Cristoloveanu and SS Li, Electrical Characterization of Silicon-on-Insulator Materials and Devices (Dordrecht, The Netherlands: Kluwer Academic Publishers, 1995).

Michael L. Alles, PhD, is the director of marketing and applications engineering at Ibis Technology in Danvers, MA, where his responsibilities include the identification of SIMOX-SOI material requirements, metrology, process development, and process integration support. Prior to joining the company as a device engineer in 1992, Alles worked at Harris Semiconductor as a design engineer on 256K SIMOX-SOI SRAM while pursuing his postgraduate studies. He holds PhD and MS degrees in electrical engineering from Vanderbilt University in Nashville, TN. (Alles can be reached at 978/539-2235 or mike_alles@ibis.com.)

Robert P. Dolan, vice president of wafer manufacturing at Ibis Technology, is responsible for all aspects of SIMOX-SOI wafer production and product characterization. He has 20 years of experience in ion implantation, including 16 years devoted to the engineering of oxygen implanters and the manufacturing of SIMOX-SOI wafers. Before joining Ibis, Dolan was with Eaton's semiconductor equipment division, where he worked on the development of NV200 oxygen implanters and the SIMOX process. (Dolan can be reached at 978/539-2213 or bob_dolan@ibis.com.)

Maria J. Anc, PhD, is a research program manager at Ibis Technology focusing on SIMOX material formation and characterization. With 20 years of experience in device, process development, and advanced material characterization, she has worked at the Massachusetts Microelectronics Center in Westboro and the Foxboro Co. Microsensor Research Center in Foxboro, MA. She received her PhD in electronics from the Institute of Electron Technology in Warsaw, Poland. (Anc can be reached at 978/539-2246 or maria_anc@ibis.com.)

Michael A. Mendicino, PhD, is a principal staff engineer scientist at Motorola's digital DNA laboratories in Austin, TX, where he works on advanced device technologies for high-performance CMOS applications. After receiving a BS from Ohio State University (Columbus) in 1989 and an MS and a PhD in chemical engineering from the University of Illinois (Champaign-Urbana), Mendicino completed a two-year assignment at Sematech, where he was a project leader responsible for the characterization and development of thin-film SOI materials. He is a member of the Institute of Electrical and Electronics Engineers. (Mendicino can be reached at 512/933-8424 or ra1458@email.sps.mot.com.)

MicroHome | Search | Current Issue | MicroArchives
Buyers Guide | Media Kit