Building Copperopolis II

Evaluating wafer reclaim techniques in emerging copper processes

Christopher Beaudry and Satoru Takada, Kobe Precision; and Tetsuo Suzuki, Kobe Steel

All wafer reclaim companies must address the issue of copper removal while protecting their current processes from copper contamination.

Several key developments in the semiconductor industry have led to the unveiling of the first copper interconnect­based devices. As the advantages of copper over aluminum drive the semiconductor industry to the widespread use of copper, a big concern is the cost of developing and sustaining copper-related technologies. Regardless of the materials employed, a significant percentage of semiconductor manufacturing costs goes toward the purchase of test wafers. Since the value of a single wafer containing high-end devices can represent tens of thousands of dollars of potential revenue, the importance of using high-quality test wafers throughout a manufacturing facility to maximize yields is unquestionable.

The recent three-year industry downturn has forced many companies to focus on reducing their running costs. During this time, reclaiming used wafers for reuse emerged as an acceptable way to substantially reduce million-dollar budget outlays for test wafers. The reclamation cycle forms a loop in which used wafers are sent to a reclaim vendor, processed to meet fab specifications, and sent back to the customer for use as test wafers. A wafer reclamation process involves essentially three main steps: removing the unwanted materials, polishing, and cleaning.

To date, many process engineers have been reluctant to reclaim wafers processed with copper for fear of cross-contamination. Because copper has long been considered a killer metal, its introduction into the IC fabrication process presents a formidable challenge. Copper diffuses in silicon at relatively low temperatures and in unwanted locations, thus posing the danger of device failures. This has led fabs using copper to impose stringent copper-specific protocols to avoid cross-contamination in all facets of the manufacturing process. Reclaim companies must also adopt such strategies to accommodate and participate in the transition to copper. This article addresses the challenge that copper processing poses to wafer reclamation and discusses strategies developed by Kobe Precision (Hayward, CA) to optimize the reclaim process.

Risks Versus Rewards

The concept of cutting test wafer costs is not new. Basically, two approaches have been taken: to reduce the number of test wafers used and to use them as many times as possible. The implementation of statistical process control programs and equipment improvements are examples of how the industry has reduced the overall number of test wafers. In recent years, the concept of extending the usable life of test wafers has received much attention, and many manufacturers have implemented internal test wafer­recycling programs. These programs consist of process loops that range from simple cleaning and reuse steps to extremely complex strategies. A simple process flow may require that wafers be used for only one purpose. More-complex programs may involve the categorization of all wafers and their upgrading or downgrading according to test wafer specifications. Since the number of processes that require the use of test wafers is vast, many different types of wafers--including bare, patterned, metal, nonmetal, and combination wafers--are produced, making it difficult to handle all of them.

Although internal test wafer­recycling programs are an important part of the overall goal of reducing costs, the ability of fabs to recover used wafers internally is quite limited. This has led to the establishment of the wafer reclamation industry, whose objective is to remove all nonsilicon materials from the wafer surface and to recondition wafers to "superclean" standards. Today, reclaim companies can recover a large percentage of wafers that would have gone into the scrap heap a few years ago, leading to significant savings.

In order to further reduce costs, a larger percentage of used wafers must be reclaimed than is presently the case. As shown in Figure 1, if a company processing 200-mm wafers has 100,000 wafer starts per month and a 30% test-wafer-to-prime-wafer ratio, it can save more than $400,000 per month (nearly $5 million per year) by increasing the proportion of reclaimed wafers to total test wafers from 20 to 75%. The ratio is defined as:

reclaimed wafers

However, the increasing implementation of copper in semiconductor manufacturing, combined with the trend to reduce costs, presents a challenge to the wafer reclaim industry. All reclaim companies must address the issue of copper-wafer reclamation while protecting their current processes from copper contamination. If they exclude copper wafers from the reclamation loop, they will decrease the percentage of used wafers being reclaimed, forcing overall higher costs on semiconductor manufacturers.

 

Figure 1: Illustration of the potential savings in a 200-mm fab achieved by increasing the proportion of reclaimed to total test wafers.

The financial impact of reclaiming copper wafers will increase as the industry shifts to 300-mm manufacturing. The surge of activity in 300-mm process development indicates that in the near future large numbers of 300-mm test wafers will be required. Those semiconductor manufacturers and toolmakers who use reclaimed 300-mm test wafers will realize substantial savings. Copper, already an integral part of 300-mm development, will continue to play a large role as 300-mm technology spreads. Because of the high cost of prime test wafers, the development of profitable strategies for reclaiming copper test wafers will become increasingly important as fabs open 300-mm production lines.

The Reclaim Challenge

Wafer reclaim companies have always found it difficult to design processes to handle the many types of wafers that fabs wish to reclaim. As wafer manufacturers begin to infiltrate copper wafers into the reclamation loop either intentionally or inadvertently, reclaim companies will have to deal with such wafers. To reach the theoretical limits of reclamation efficiency, copper reclaim programs are required.

Because of copper cross-contamination issues, most reclaim vendors avoid processing copper wafers. Those who do process such wafers rely on segregating them according to customer and by performing incoming visual inspections. However, such segregation methods are an inadequate response to the risks of contamination, since "stealth" copper wafers slip into noncopper process baths and quietly cause problems. Until real-time copper monitoring methods in chemical baths are developed, reclamation processes are required that are robust enough to deal with stealth copper wafers in noncopper chemical strip baths and processes.

It is risky to employ traditional film-removal methods, such as chemical and mechanical techniques, when dealing with copper wafers. Chemical techniques involve the immersion of wafers in a series of chemical baths to strip the film materials and etch the silicon. Mechanical techniques, on the other hand, physically remove films and silicon by placing the wafer between two counterrotating metal plates and lapping away material by means of slurries. Although this technique effectively removes films from the front and back surfaces of wafers, it does not remove contamination on the wafer edge. Thus, if copper film is deposited on the edge or the edge is contaminated, the mechanical technique is ineffective, endangering downstream processes. Furthermore, because of the mechanical nature of conventional lapping, a deep damage layer is created on the wafer, requiring significant silicon removal in subsequent processing steps to recover the original wafer finish.

Optimizing the Reclaim Process

Chemical Processing. Although the segregation of copper wafers is not foolproof, identifying copper wafers at the incoming step will continue to play an important role in wafer reclamation. Labels, copper-specific laser scribes, and special copper-dedicated shipping boxes are simple examples of the kinds of gates that can direct copper wafers to the correct process flow. After arriving at the reclaim site, an identified copper lot must be directed to a dedicated film-removal process that is designed to remove virtually all nonsilicon materials and reduce copper to an acceptable amount (<10¹⁰­10¹³ atoms/cm², depending on the subsequent process design). The dedicated film-removal process lessens the risk of cross-contamination downstream. The specific design of the downstream process and its effectiveness in removing copper helps determine the acceptable level of metal contamination at this point in the reclaim process.

Chemical solutions to remove film from a wafer typically contain hydrofluoric acid. However, while hydrofluoric acid solutions effectively remove most types of metal from the wafer surface, they tend to promote copper deposition on bare silicon when copper is present in the solution.¹ Although the exact mechanism by which this deposition occurs is still under investigation, the general electrochemical reaction is:

2Cu²⁺ + Si 2Cu + Si⁴⁺

whereby the Cu²⁺ is reduced to Cu and Si is locally oxidized to Si⁴⁺. In other words, the copper ions in the solution become electrochemically plated on the wafer, thereby contaminating the surface.

Because a copper strip bath contains a significant amount of copper, redeposition will occur even if the copper is initially removed. Furthermore, hydrofluoric acid solutions etch the oxidized silicon, causing severe pitting of the wafer surface, as shown in the reaction:

Si⁴⁺ + 6HF H_²SiF_⁶ + 4H⁺

Four tests were performed to evaluate the ability of various chemical techniques to prevent copper redeposition. In test 1, the results of which are depicted in Figure 2, a clean, bare wafer was immersed for just 3 minutes in a solution containing equal parts of hydrofluoric acid and water that had been intentionally contaminated with 0.2 wt% of copper. After immersion, large amounts of copper appeared on the wafer surface. The amount of copper in solution was approximately equivalent to the amount of copper in solution after 200 wafers with a 1-µm-thick copper film have been stripped, demonstrating clearly that even a small number of stealth wafers can have a deleterious effect on a reclaim facility.

Figure 2: Wafer with a large amount of copper on the surface after having been immersed for 3 minutes in a hydrofluoric acid solution that had been contaminated with 0.2 wt% of copper.

In tests 2 through 4, a clean bare wafer was immersed for 10 minutes in a solution containing equal parts of hydrofluoric acid and water (and various additives) that had been intentionally contaminated with 0.2 wt% of copper. Suitable additives were selected carefully based on determining the cleanliness of the additives themselves and any adverse effects they might have.

In test 2, the results of which are illustrated in Figure 3, the electrochemical reaction resulting in copper redeposition was suppressed through the addition of an effective oxidant. This method effectively oxidized the copper ions, which impeded redeposition. In test 3, the results of which are shown in Figure 4, copper ions were "held" in the solution with the addition of a suitable chelating agent. The chelating agent attracted the copper in solution by forming a complex with copper ions. Such a copper-chelate complex is stable in acidic solutions and, therefore, not attracted to the wafer surface. Although the solutions used in tests 2 and 3 caused less damage to the silicon wafer than that in test 1, the wafer surface still showed visible signs of degradation.

 

Figure 3: Wafer on which copper redeposition was impeded by the oxidation of copper ions still shows visible signs of degradation.

Figure 4: Wafer with visible signs of degradation on which copper ions were "held" in the solution with the addition of a chelating agent.

Finally, a fourth test was performed that combined both the oxidant and chelating approaches. In this test, the results of which are shown in Figure 5, some copper ions in solution were suppressed and the remaining ones were complexed, producing the best visible result.

These tests show that it is possible to improve chemical stripping technologies to reduce inadvertent copper cross-contamination of noncopper wafers. With the introduction of appropriate additives, traditional chemical stripping technologies can withstand a large spike of copper contamination, protecting all wafers within the facility. For example, after a clean wafer was immersed for 10 minutes in an optimized noncopper stripping solution that had been contaminated with copper, the concentration of copper on the wafer surface was on the order of 10¹³ atoms/cm², an improvement of at least 200% over wafers that had been stripped by nonprotected chemistry methods.

 

Figure 5: Wafer from a solution combining an oxidant and a chelating agent, in which some copper ions were suppressed and the remaining ones were complexed, producing the best visible result.

To assess the worst-case scenario, this sample was measured after the wafer had been immersed in the first bath in the stripping process. Subsequent process baths can reduce the level of copper cross-contamination still further. It is also possible to theoretically design different levels of copper protection by determining the appropriate amounts of additives to handle different spike levels (e.g., by gauging the number of wafers with an assumed copper-film thickness).

The initial results of this study indicate that copper-protection techniques can effectively be tailored to handle thousands of misdirected wafers. While it is difficult to accurately quantify the advantages of an optimized noncopper stripping solution over a nonprotected chemistry because extensive copper plating results in inaccurate surface concentration calculations, it is nonetheless clear that copper deposition in hydrofluoric acid­based chemistries can be suppressed significantly.

Chemical and Mechanical Processing. A traditional mechanical process was then modified to remove additional material from the surface and edge of reclaim wafers. First, an edge process removes a few microns of silicon from the edge and the flat or notched surface of the wafer. Second, a patented lapping process removes a few microns of silicon from the front and back surfaces of the wafer, causing only minimal subsurface damage.² As seen in Figure 6, combining chemical and mechanical technologies results in a robust process that removes a minimal amount of silicon. Because this process typically removes ~22 to 25 µm of material, it can enable companies to extend the life of their test wafers by recycling them repeatedly.

 

Figure 6: Diagram of an optimized copper-specific process consisting of chemical and mechanical steps, which ensures unwanted material removal from all wafer surfaces.

Copper-Specific Stripping. To further optimize the copper wafer reclamation process, a highly efficient copper-specific stripping process was developed by which surface concentrations of copper on the order of 10¹⁰ atoms/ cm² were obtained (copper films were originally 1.0 to 5.0 µm thick). To confirm that copper redeposition in a used stripping solution had been prevented, clean wafers were immersed in an optimized stripping solution contaminated with 0.2 wt% of copper. This test also resulted in a copper surface concentration of <10¹⁰ atoms/cm².

The validity of the overall final process was confirmed by processing and sampling a few lots of various types of copper wafers to determine trace-metal levels. After final cleaning, samples from these copper lots as well as from noncopper lots, which had undergone their respective copper and noncopper removal processes, were analyzed using vapor-phase desorption/inductively coupled plasma mass spectrometry. This analysis, the results of which are presented in Figure 7, showed that all the wafers studied contained <10¹⁰ atoms/cm² of copper and all other metals for which tests were conducted. More importantly, these wafers fell within typical noncopper process capability levels.

Controlling Copper Bulk Contamination

Although the technique of combining an optimized chemical process and a modified mechanical process can eliminate contamination on or near the wafer surface, the critical issue of copper bulk contamination remains. What if the bulk of the wafer is contaminated with copper? The rapid diffusion of copper in silicon at relatively low temperatures can cause the metal to form deep-level traps for carriers. This issue has deterred chipmakers from shifting quickly to the fabrication of copper devices. However, the development of effective diffusion barriers has allowed manufacturers to overcome this problem.

 

Figure 7: Copper levels on wafers that underwent chemical and mechanical processing were <1010 atoms/cm2 in both noncopper and copper lots.

Currently there is no reasonable and cost-effective method for nondestructively measuring bulk metal contamination on a wafer-for-wafer basis. Consequently, reclaim vendors must rely on their customers to weed out wafers that have potentially been bulk contaminated, including those that have copper deposited directly on a bare silicon surface. Since there is as yet no way to know whether this type of wafer has been heat-treated or whether it has gone through any process that would encourage copper diffusion into the bulk, it is impossible to assess the robustness of eventual processes that may be designed to alleviate the problem. The only current solution is to develop a tool that can measure bulk contamination on every wafer. However, until such a tool is developed, the elimination of such wafers from the reclamation flow is critical.

A better solution is to design a wafer control protocol that prevents bulk diffusion into test wafers by means of barriers such as silicon nitride and tantalum or tantalum nitride, which are effective in preventing copper diffusion. The use of such diffusion barriers on all wafers in a copper facility would prevent the metal from being deposited directly onto silicon. Essentially, these materials act as a seal to keep copper where it belongs. Since many diffusion-barrier materials are utilized in device manufacturing, it makes sense to extend their use to copper wafer reclamation. By depositing a diffusion barrier on all wafer surfaces, the potential for bulk contamination could be significantly reduced, if not eliminated. Assuming that the barrier film has not been etched away during the course of the wafer's life, it may be possible to visually confirm at an incoming inspection step whether or not a diffusion barrier has been deposited on all sides of the wafer. This requires that reclaim vendors and their customers cooperate with one another.

Conclusion

The introduction of copper technologies must be addressed by the silicon wafer reclaim industry. Kobe Precision has developed and implemented methods to protect all noncopper wafers processed in its facility from inadvertent copper cross-contamination. An optimized process design, combining chemical and mechanical techniques, can efficiently remove copper and virtually any other film from reclaim wafers without causing cross-contamination and excessive silicon removal. Furthermore, these techniques have been extended in order to develop a copper-specific process.

Although the results presented in this article are limited, they support the case for further investigation. Although it is now possible to reclaim copper wafers, it is still imperative to refine the process as the industry expands its copper learning curve. The first step in this process is a conservative one: to gain a thorough understanding of the customer and vendor issues involved in reclaiming copper wafers. Success in this field will depend heavily on vendor-customer interaction and a mutual understanding of the challenges and financial benefits of copper wafer reclamation.

Acknowledgments

The authors would like to thank Jack Thomas of AMD (Sunnyvale, CA) for reviewing the manuscript of this article and for his insightful suggestions. They also wish to thank Paul Miller and Andreja Dugacki of Kobe Precision for their help in the preparation of this article.

References

1. H Morinaga, M Suyama, and T Ohmi, "Mechanism of Metallic Particle Growth and Metal-Induced Pitting on Si Wafer Surface in Wet Chemical Processing," Journal of the Electrochemical Society 141 (1994): 2834­2841.

2. Process for recovering substrates, U.S. Pat. 5,855,735, 1999.

Christopher Beaudry, PhD, is a process development engineer at Kobe Precision (Hayward, CA). He is responsible for the development and implementation of copper and 300-mm-wafer reclamation processes. Previously, he worked at Komatsu Silicon America as a process engineer focusing on silicon wafer cleaning. The author or coauthor of more than 15 papers, Beaudry is a member of the Electrochemical Society. In 1997 he received a PhD in ceramic science and engineering from Rutgers University in New Brunswick, NJ. (Beaudry can be reached at 510/487-3200 or cbeaudry@ kpi.com.)

Satoru Takada is a process engineering manager at Kobe Precision, where he has established a patented silicon wafer reclamation process. He has more than 10 years of experience with development and process engineering in the silicon wafer and hard-disk substrate industries. He has an MS from the Kyoto Institute of Technology in polymer science focusing on photospectroscopy. (Takada can be reached at 510/487-3200 or stakada@kpi.com.)

Tetsuo Suzuki, PhD, is a senior researcher in the technical division of Kobe Steel in Kobe, Japan, the parent company of Kobe Precision. He has 14 years of experience in applied surface chemistry and R&D on advanced materials. Since 1995 he has worked in collaboration with Kobe Precision on the development of wafer reclamation processes, focusing on chemical etching, chemical-mechanical polishing, and cleaning. In addition, Suzuki spent six years in the field of molecular spectroscopy of free radicals at the Institute for Molecular Science in Okazaki. He received a PhD in physical chemistry from Tokyo Metropolitan University. (Suzuki can be reached at +81 78 9925543 or te-suzuki@rd.kcrl.kobelco.co.jp.)