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Building Copperopolis IIUsing a wafer backside spin process to eliminate contamination in copper applicationsIsrael Ybarra Jr., Sematech; and Gaurav Virendra Gupta, SEZ A spin-process technique prevents back-surface particle contamination of the process chuck, creates an edge exclusion zone, and optimizes the copper/barrier material interface. As device features shrink below 180 nm, interconnect delay becomes critical, making low-resistivity copper highly desirable. However, because copper migrates very quickly in silicon, its successful integration in future IC devices will require stringent prevention of copper cross-contamination from deposition equipment, electroplating tools, chemical-mechanical polishing (CMP) equipment, and all metrology tools that handle copper-processed wafers. Based on extensive data, this article investigates the spin-process contamination elimination (SpCE) technology developed by SEZ (Villach, Austria and Phoenix), an effective means of eliminating copper from the wafer backside, bevel/edge, and frontside edge exclusion zone (0.5–3.0 mm). The article also presents data that demonstrate the effectiveness of this application for advanced prelithography cleans. These data, obtained through standard and experimental copper/low-k device production at Sematech (Austin, TX), highlight the reliability and potential cost-effectiveness of implementing SpCE technology and confirm the feasibility of using existing (noncopper) process equipment in conjunction with copper applications. Preventing Copper Cross-Contamination The transition from aluminum to copper contacts and from oxide to low-k dielectric interconnect materials has spurred a fundamental shift in back-end processing toward the dual-damascene approach.1 Low-k dielectrics not only improve speed by lowering resistance-capacitance (RC) delay but also reduce crosstalk noise and alleviate power dissipation concerns.2 While new materials are being investigated as potential replacements for thermal silicon dioxide (SiO2, k = 3.9) to reduce the capacitance component of RC interconnect delays, copper is expected to replace aluminum as the main on-chip conductor. The two main components of the cost equation are the interconnect layer and the stack. A copper interconnect layer costs 20% less than a comparable aluminum one, and a more dramatic cost reduction will be realized when copper devices are designed and built that require fewer layers than their aluminum counterparts.3 Offering resistance of <2.0 µ The National Technology Roadmap for Semiconductors (NTRS)
established target levels for critical and other surface metals. For starting
material requirements, target levels for copper must be Many production facilities do not possess a metrology system that can effectively measure critical metals at such low levels. Consequently, it has become increasingly necessary to clean wafers to prevent a combination of problems, such as particles, stress-induced bow and warp, and copper contamination. In conjunction with a range of chemical etchants, including oxidizers, reduction agents, and cleaning solutions, the spin-process contamination elimination technology effectively addresses the wafer-cleaning challenge. As semiconductor production facilities move into the copper age, serious contamination monitoring and control procedures must be rigorously implemented. Noble metal contaminants such as copper often prove to be the leading cause of device degradation.8 In the experiments conducted at Sematech, the lack of dedicated copper tools meant that copper lots could be processed only one day per week on nondedicated tools, causing increased cycle times. However, even if manufacturing facilities possess a dedicated copper tool set, postcopper tool cleaning and monitoring by means of total reflection x-ray fluorescence spectroscopy (TXRF) and vapor phase decomposition inductively coupled plasma mass spectrometry (VPD-ICP-MS) add to production costs. SEZ has addressed the problems associated with the transition to copper processing by developing the Spin-Processor 203. With its novel single-wafer, back-surface SpCE technology, this tool processes patterned wafers directly from copper tools and certifies processed lots as copper free for subsequent processing in noncopper tools, thus reducing cycle times and monitoring analysis costs. The spin-processor picks wafers from a lot or cassette that is potentially contaminated with copper, loads and unloads them in and out of the process chamber with edge-contact-only grippers, and places them into a clean cassette by means of a clean end effector. This sequence of steps establishes the point of isolation within the fab, thus minimizing the risks associated with reducing the frequency of contamination monitoring by TXRF and VPD-ICP-MS. Sematech Development Activities Sematech provides custom copper processing services, including standard baseline materials, several novel processes, and material and tool development activities. For example, while running wafers through the MicraScan III deep-ultraviolet (DUV) step-and-scan lithography system from SVGL (Wilton, CT), Sematech discovered that the tool experienced reduced wafer throughput and increased downtime performance because of a wide variety of incoming wafer quality issues. The frequency and duration of tool downtime associated with chuck cleaning had risen to unacceptable levels because of incoming contamination transferred from the back surface of processed wafers. Figure 1 shows that the introduction of the spin-process technique on May 26, 1999, had a beneficial impact on chuck cleaning frequency. A prelithography visual inspection of incoming wafer backsides under broadband bright light conditions was implemented. Table I illustrates the severity of the wafer quality problem before the introduction of the spin process and the immediate and complete improvement in quality as a result of this process.
Table I: An immediate and complete improvement in wafer quality resulted by introducing the spin-process contamination elimination technique.
Tests on the optimal use of chemicals in the spin-process tool were also performed at Sematech. The spin-process technique uses a liquid chemical solution dispensed on the surface of a spinning wafer to remove copper contamination from the backside and bevel/edge. The process also may be used to remove thermal oxide or nitride films from the wafer backside and controlled to perform a precision wraparound film removal etch (an edge exclusion zone) on the wafer frontside. Copper particles imbedded within the oxide are effectively eliminated by removing approximately 200 Å of SiO2 with a chemical blend that includes hydrofluoric (HF) acid. The wafer is suspended device-side down above the process chuck on a nitrogen cushion using the Bernoulli principle and is restrained on the chuck with locating pins at the wafer perimeter. The wafer is rotated with the chuck while the etch solution is dispensed from a radial oscillating overhead nozzle. The continuous fresh supply of chemical medium, applied in a custom dispensing pattern, is designed to ensure a uniform etch rate over the wafer surface and has been optimized to reduce the stress-induced bow and warp associated with several experimental copper/low-k products.9,10 Solutions are recipe selected from three local chemistry cabinets and may be routed to the drain or recirculated. Controlling the simultaneous radial and tangential etchant flow along with the etchant viscosity and composition enables the removal of contaminants, particles, and film from the wafer backside, bevel/edge, and front exclusion zone without the risk of damaging device structures. Tests were performed using nitric acid (HNO3), which, in its concentrated form, is a rapid etchant of copper. An oxyacid and, therefore, a strong electrolyte, HNO3 is a powerful oxidizing agent that is considered 100% ionized in aqueous solution (H2O). The oxidation number of N in HNO3 is +5. The most common reduction products of nitric acid are NO2(where the oxidation number of N = +4), NO (where the oxidation number of N = +2), and NH4+ (where the oxidation number of N = –3).11 Half reactions yielding common reduction products are: NO3–(aq)
+ e– + 2H+(aq) NO3–(aq)
+ 3e– + 4H+(aq) The first reaction equation predominates when concentrated (70%) HNO3 reacts with copper: Cu(s) + 4H+(aq) + 2NO3–(aq)
The second reaction equation predominates when copper reacts with a mixture of equal volumes of concentrated HNO3 and H2O: 3Cu(s) + 8H+(aq) + 2NO3–
(aq)
Nitric acid oxidizes most metals to their corresponding cations. Since the stronger oxidizing agent in HNO3 is not H+ but the NO3– ion, the reduction product is not H2 but NO2, NO, or NH4+.11–13 While concentrated nitric acid is an extremely rapid etchant of copper and HF is slow, solutions of HNO3:HF are relatively fast and more controllable than straight HNO3. The removal rate is reduced by increasing the ratio of HF.8 The standard production recipe for a combination of incoming wafer issues, including copper contamination, is sequential HNO3/HF (dilute) repeated twice, which etches ~200 Å of silicon dioxide from the back surface. During spin-process tests at Sematech, a wafer with 1 kÅ of copper seed deposition was processed on the frontside and analyzed by TXRF. Table II lists the copper contamination results of that demonstration and compares them to the results for iron, nickel, and zinc. Two of three sites on the wafer were below the detection limit for copper (1.0 x 1010 atoms/cm2), while the wafer average of 1.6 x 1010 atoms/cm2 was far below the failure threshold of 50 x 1010 atoms/cm2 for copper at back-end-of-line operations.
Table II: TXRF analysis of wafer frontsides detailing how much copper from a 1-kÅ seed layer remains after the spin-process technique has been performed (measurements in x1010 atoms/cm2).
Wraparound Etch Process Results The spin-process technique addresses copper contamination issues in three specific wafer regions: the backside, edge, and frontside exclusion zone. During the deposition process, the thickness of the copper layer gradually changes from approximately 16 kÅ at 3 mm from the wafer edge to nothing at the edge itself. Because of this gradual transition, it is difficult to consistently define a copper-free zone for subsequent operations. Device degradation from cross-contamination results when wafer transportation cassettes or staging systems contact the edge or exclusion zone before a decontamination sequence has been performed. The spin process effectively removes copper from the exclusion zone and defines a clear, immediate transition between the copper film and the copper-free exclusion zone on the wafer frontside. This enables fabs to work with other equipment makers (such as lithography toolmakers) to define wafer transportation and staging methodologies that do not overstep this copper-free zone. The resulting combination of decontaminated wafers and proper handling methods enables fabs to avoid capital costs by not having to procure additional equipment for a dedicated copper line. In addition, by ensuring that copper does not contaminate subsequent operations, the spin-process technique results in an increase in device yields. The failure to remove copper from the exclusion zone may not be detrimental to the device at every process step, because copper diffusion through tantalum nitride is minimal below 400°C.14 During CMP processing, however, any cross-contamination from the copper film or residue on the bevel/edge remains a serious concern. The scanning electron microscopy (SEM) tilted cross-section image in Figure 2 illustrates the ability of the spin-process wraparound technique to remove copper film from the wafer frontside and expose the tantalum barrier layer from the bevel/ edge to the copper film, resulting in an exclusion zone of 2.35 mm. The clearly defined line of transition from copper to tantalum results from chloride crystal formation on the partially etched copper, which is produced by a mixture of H3PO4:H2O2:HCl:H2O in a concentration ratio of 2:3:0.1:5. The amount of undercut may be adjusted from 0.5 to 3.0 mm. (The particles in the exclusion zone that are visible in the SEM image were produced during SEM sample preparation and are not related to chemical processing.) Figure 3 is an edge-on cross section representing the transition from the 10 kÅ of electroplated copper film to the clean tantalum barrier over a horizontal distance of 0.015 mm (15 µm). This sample was etched by H3PO4:H2O2:H2O in a concentration ratio of 1:1:18.
Wraparound etch experiments have been performed on wafers with combinations of copper seed and electroplated copper over various barrier layer materials, including tantalum, tantalum nitride, titanium, and titanium nitride. Copper was also deposited directly on bare silicon and silicon dioxide. These experiments were designed to provide a comparative analysis of the effects of various chemical solutions on the extent of the exclusion region and the quality of the transition in terms of residue and corrosion. Metal corrosion is an electrochemical process composed of anodic (metal oxidation) and cathodic (reduction) reactions that occur on the metal surface.15 On a copper film, the anodic and cathodic current densities may vary arbitrarily from point to point as long as the total anodic and cathodic currents are equal. This variation is associated with local differences in pH and surface composition (defects). Corrosion can be controlled by slowing down either the anodic or the cathodic reaction and by controlling the environment surrounding the reaction surface. Four chemical mixtures were evaluated for their ability to remove copper from the wafer backside, bevel/edge, and frontside exclusion zone: Mixture A--H2O2:HCl:H2O (1:4:20) Mixture B--HNO3:H3PO4:H2O (2:1:2) Mixture C--H3PO4:H2O2:HCl:H2O (2:3:0.1:5) Mixture D--H3PO4:H2O2:H2O (2:3:5) Although the relatively high concentrations of HCl in mixture
A and HNO3 in
mixture B cause a slight irregularity of the etch transition line, the
ability of these mixtures to remove copper is very aggressive, producing
a Chemical solution C differs from D in that it is spiked slightly with HCl, which speeds the chemical reaction. Figure 4 illustrates the effect of chemical solution C on titanium (left) and titanium nitride (right) in the copper seed etch process. The titanium barrier layer shown in the left-hand image indicates very slight corrosion at the copper edge transition while the titanium nitride barrier shown in the right-hand image is corrosion free. Chemical mixture D has a less-aggressive effect than the other solutions (particularly A and B). Lacking HCl, mixture D produces the cleanest result, as illustrated in Figure 5 by the smooth and straight transition between copper and the tantalum nitride barrier (left) and between copper and the titanium barrier (right). The slight bubbling reaction visible on the copper layer near the transition in the right-hand image can be eliminated by adjusting the nitrogen flow rate around the wafer edge where the reaction takes place.
Figure 4: Images illustrating that chemical solution C results in very slight corrosion at the copper edge on the titanium barrier (left) and no corrosion on the titanium nitride barrier (right).
Figure 5: Images illustrating that chemical solution D produces a smooth and straight transition between copper and the tantalum nitride barrier (left) and between copper and the titanium barrier (right). Microroughness and Bevel Profilometry The experiments conducted at Sematech tested the effectiveness of the spin process to create an abrupt transition between the copper film and the wafer exclusion zone. To accomplish this, wafers were analyzed for microroughness and step height (the transition between the copper film and the barrier layer) using a NanoScope III with a Dimension 5000 multimode atomic force microscope in tapping mode (Digital Instruments, Veeco Metrology Group, Santa Barbara, CA). Each copper layer was analyzed in several locations close to the wafer edge. An appropriate flatten/plane fit filter was applied to the image to filter out the tilt, bow, and wave caused by the scanner. The profile of an unprocessed copper/tantalum control wafer presented in Figure 6 (left) shows a gradual transition between copper and the tantalum barrier material. Over a distance of 15.938 µm from the copper/tantalum boundary, the copper thickness gradually increases to only 12.72 Å on a 1-kÅ copper seed layer. Figure 6 (right) plots several waves on the edge of the wafer that were visible in the AFM-captured images. Figure 7, based on testing the wafer with a Dektak3 ST stylus profiler (Veeco, Plainview, NY), shows that before introducing the SpCE technique the copper had reached a thickness of 1 kÅ at a distance of 750 µm from the wafer's edge.
Figure 6: Image of an unprocessed copper/tantalum
control wafer showing a gradual increase in copper thickness to only
12.72 Å over a distance of 15.938 um on a 1-kÅ copper
seed layer (left) and several waves on the edge of the wafer captured
in AFM images (right).
Microroughness was measured using a sequence of equations. In the equation Ra = average roughness (average of the deviations from the center plane), where Zi is the current Z value, Zcp is the Z value of the center plane, and N is the number of points within the given area. In the equation rms is the root-mean-square roughness (standard deviations of the Z [height] value within a given area), where Zave is the average value within the given area, Zi is the current Z value, and N is the number of points within the given area. Maximum roughness (Rmax) is the difference between the highest and lowest points within the captured area. For any given image, the highest resolution, 512 points per line horizontally, is used for AFM imaging. That is, both a 1-µm horizontal line in a 1.0 x 0.5-µm image and a 20-µm line in a 20 x 10-µm image contain 512 points, whereby the pixels are further apart in the larger image than in the smaller one. In both cases, 512 points is the standard from which changes in height are calculated. However, the AFM tip does not pick up small changes in height for the points that are very close to one another within an image. Thus, the rms value in a 1.0 x 0.5-µm image is larger than in a 20 x 10-µm image. This is typically observed for smooth surface samples. Table III illustrates the surface microroughness of the copper, tantalum, and interface regions of a wafer with copper seed over tantalum before and after the SPCE application was performed. Roughness measurements of the interface region composed of copper and tantalum were taken after a wafer was processed with the spin-process technique and chemical solution D. Figure 8a shows the copper region before the introduction of the technique. Figure 8b depicts the rough interface surface between the copper and tantalum regions after the spin process. Figure 8c shows the tantalum region with a smoother surface after the spin process, and Figure 8d is an enlarged scan image of the copper/tantalum interface region after the process was conducted. The copper/tantalum interface region was <2.0 µm from the wafer edge on the 1-kÅ copper/tantalum seed, as illustrated in Figure 9. Given the desired abrupt transition from copper to tantalum depicted in Figures 8 and 9, the spin-process technique was shown to provide adequate profile and roughness at the copper/tantalum interface. As shown in Figure 10, an even greater degree of roughness at the transition area was seen where an oxide barrier interfaced with the copper film.
Table III: Surface microroughness of 1 kÅ of copper seed over tantalum before and after performing the spin-process contamination elimination technique.
To confirm the results of the AFM scans presented in Figures 8d, 9, and 10, additional tests were performed using a P-2 profilometer (KLA-Tencor, San Jose), the results of which are shown in Figures 11, 12, and 13. Overall, the P-2 profilometer plots are consistent with the AFM scans, all of which show a sharp transition from the barrier material to the copper. Figure 11, for example, shows that the copper step height on oxide is ~1 kÅ when the wafer is etched with chemical solution D. Other combinations of various barrier materials and chemical solutions were tested. Figure 12 shows a 1-kÅ-thick copper layer over tantalum nitride etched with chemical solution C, while Figure 13 shows a 1-kÅ-thick copper layer over oxide, also etched with chemical solution C.
Roughness measurements for copper, oxide, and interface regions of a wafer with copper seed over oxide are summarized in Table IV. Comparing Tables III and IV, the bulk copper seed roughness varied from ~11 to 48 Å rms while the copper interface roughness varied from ~7 to 64 Å rms. The 1-kÅ-thick copper/tantalum control wafer with the bevel unprocessed by the spin technique had the lowest interfacial roughness of ~7 Å rms. The same wafer processed by the technique, on the other hand, revealed an interfacial roughness of ~60 Å rms. Additionally, the spin-process wraparound technique, which removes copper from the wafer frontside and exposes the tantalum layer from the bevel/edge to the copper film, resulted in an ~10-kÅ copper profile with an interface transition of 15 µm.
Table IV: Surface microroughness of 1 kÅ of copper seed over oxide after performing the spin-process technique. All the different metal barriers used in the experiment (tantalum, tantalum nitride, titanium, titanium nitride, and oxide) left a well-developed interface region with an abrupt transition from metal to its barriers. The spin-process technique, in conjunction with newly developed chemistries combining H3PO4, H2O2, HCl, and/or H2O, results in a sudden, beneficial transition between the barrier films and the 1-kÅ copper seed.
Conclusion The spin-process technology was able to effectively eliminate copper cross-contamination in the dynamic semiconductor R&D environment at Sematech. Its benefits include a reduction in cycle times for copper and noncopper products and a reduction in production costs because TXRF monitoring can be dramatically reduced for copper lots processed on noncopper tools. Because of the technology's versatility, it has been formally implemented as the standard prelithography clean process for all products. Besides being able to provide a copper-free status to all copper/low-k interconnect products, this spin-process technique prevents back-surface particles and residue from transferring from wafers to the process chuck, thereby reducing cleaning frequency and stepper downtime. Because highly porous low-k dielectric materials yield compounds that lack the rigidity of silicon dioxide, stress-induced bow and warp from metal layers may become so extreme that a wafer/vacuum seal failure occurs. The spin-process technique has demonstrated that it can normalize wafer flatness as measured by whole wafer capacitance. Moreover, it controls copper contamination by etching the backside of a spinning wafer and creating an adjustable edge exclusion zone through a frontside wraparound technique. The spin-process technology enables the selection and control of chemistries that optimize the transition between copper and the underlying barrier material. Finally, the edge exclusion may be adjusted over a linear range of 0.5–3.0 mm with corrosion-free processing. Acknowledgments The authors wish to thank Patrick S. Lysaght, Asmita Shah, Joe Bennett, and Ellwood Smith of Sematech's Advanced Tool Development Facility and Harry Sax, James L. Mello, Michael G. West, Adam Venn, and James Madsen of SEZ for their support to the research discussed in this article. References
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/cm
even when deposited in narrow trenches, copper is second only to silver
in low resistance. In contrast, aluminum alloys offer >3.0 µ
2.5
x 1010 atoms/cm2 for the 250-nm node, 
Figure 1: Number of chuck cleans per month before and after May 26, 1999, when the spin-process technique was introduced. 
NO2(g) + H2O(l)
Figure 2: SEM image illustrating the spin-process wraparound
technique that removes copper from the wafer frontside, resulting
in an exclusion zone of 2.35 mm.
Figure 3: Edge-on cross-section image showing the transition from the 10 KÅ of copper to the tantalum barrier over a horizontal distance of 0.015 mm (15 um).
,/p>
Figure 7: Graph showing that before the introduction of the spin process technique the copper reached a thickness of 1 kÅ at a distance of 750 um from the wafer edge.
Figure 9: Post-SPCE profilometry
image showing that the bevel interface region was <2.0 um from
the wafer edge on the 1-kÅ copper/tantalum seed demonstrates
the desired abrupt transition from tantalum to copper.
Figure 10: Image showing that the interface region between copper and oxide is even rougher than that between copper
and tantalum.
Figure 11: Profilometry image showing a 1-kÅ-thick copper layer over oxide when the wafer is etched with chemical solution D.
Figure 12: Profilometry image showing a 1-kÅ-thick copper layer over tantalum nitride when the wafer is etched with chemical solution C.
Figure 13: Profilometry image illustrating a 1-kÅ-thick copper layer over oxide when the wafer is etched with chemical solution C.
Israel Ybarra Jr. is a senior process technician in the Advanced Tool Development Facility (ATDF) at Sematech in Austin, TX. He is responsible for tool
acceptance benchmarking and supports complex process improvement projects for all major R&D thrusts, including contamination-free manufacturing
(CFM) and materials and bulk processes (MBP). Ybarra is investigating
surface microroughness associated with wet etch copper contamination control.
He has an associate of applied science degree in electronics and computer
technology from TSTI in Harlingen, TX.
Gaurav Virendra Gupta is responsible for the worldwide development of copper etch and contamination removal solutions at SEZ Phoenix. He has also researched
prelithography cleans for advanced applications. Before joining SEZ, Gupta was a process and applications engineer at Motorola, where he concentrated on oxide etch and local interconnect development. He received his BS in chemical engineering from Texas A&M University in College Station. (Gupta can be reached at 