Defect and Yield Analysis

Reducing baseline defect density through modeling random defect-limited yield

Julie Segal, HPL; and Linda Milor and Yeng-kaung Peng, AMD

Partitioning yield into random and systematic components and partitioning the random defect-limited yield component heightens defect reduction efforts and enhances yields.

To maintain a leading edge, semiconductor manufacturers must constantly use immature processes performed by immature processing equipment. IC processes and equipment have undergone tremendous changes over time, fostering rapid technological advances throughout the industry. The semiconductor industry has been able to double the number of transistors on a wafer and product die per wafer every two years while increasing costs by only 25­33%.¹ The results have included faster circuit speeds, lower power dissipation, and lower manufacturing costs per product. Because the prices of semiconductor products decline rapidly throughout the life of a new technology, the ability to ramp yield quickly after the introduction of new technology is fundamental to earning high revenues.

Each new technology generation involves shrinking the design rules. As a result, smaller defects become killer defects. But because die size also shrinks for the same product with the new design rules, percentage yield should remain constant.² For larger products, if baseline defect densities are not reduced, each new technology generation will see lower and lower yields for newer products. To prevent continually lower yields for larger and more-complex products as technologies evolve, fabs put significant effort into baseline defect reduction and the prevention of defect excursions. Baseline defect density is the defect level that occurs when the process is running well: there are no equipment problems or unusual defect sources. In contrast, defect excursions are high defect levels that can be attributed to a specific problem affecting only certain lots or wafers.

The implementation of baseline defect reduction methods has generated the need for new yield analysis techniques. Traditionally, reactive techniques have been used to analyze yields. That is, when a lot yields poorly, an investigation is launched to determine the cause of the excursion. This procedure has become problematic for three reasons:

• With the increasing complexity of modern process flows, the number of possible sources of yield loss has also been increasing.
  
  
• Shrinking geometries have made physical failure analysis more difficult.
  
  
• Ever-increasing competitive pressures have made the reactive approach prohibitively slow.

To surmount these difficulties, the prioritization of the sources of yield loss and proactive improvement through yield modeling have become increasingly necessary. Prioritizing the sources of yield loss through yield modeling involves yield partitioning. Overall yield can be expressed as a product of component yield loss mechanisms, or limited yields, as in the formula:

Each limited yield, Y_i, represents the final yield that would result if i were the only yield loss mechanism. Using the yield partitioning methodology, the impact of each component can be assessed, ownership can be assigned, and improvements can be tracked. This article discusses the advantages of yield modeling and various types of yield partitioning to reduce baseline defect density and enhance yields in the semiconductor fab environment.

Defect Excursion and Baseline
Reduction Strategies

In the 1970s, defect-related yield losses were primarily a result of the cleanroom environment and the lithography process. Defects were caused by dust particles in the cleanroom, mask defects left over from the mask fabrication process, imperfections in the glass used as a mask substrate, and photoresist particles that were transferred from wafers to masks through direct physical contact.³ By the mid-1980s, dust particles in the cleanroom were no longer the dominant source of defects. Meanwhile, contact printing had been replaced by projection printing, which is less vulnerable to defects.

By the 1990s, the variety of defect sources had expanded greatly; most defects on chips originated from wafer processing equipment. An example of wafer defect density distribution can be seen in Figure 1. The highest defect density in the sample is 10 times greater than the median. High defect densities, or excursions, result in wafers that produce little or no yield and are often associated with malfunctioning equipment. Without inspections, detecting defect excursions could take months, resulting in prohibitively low yields. Yield management began to encompass techniques for responding quickly to defect excursions and minimizing the time between malfunctions and their detection. Fast defect excursion detection involves the use of in-line wafer scanners and wafer position tracking, which have become common in the IC industry. Such techniques primarily eliminate wafers and lots with very high defect densities.

 

Figure 1: An example of defect density distribution by wafer.

Excursion detection strategies, while crucial for eliminating wafers with high defect densities, are insufficient for maximizing yields. To accomplish this task, it is necessary to institute baseline defect density reduction as well. As demonstrated in Figure 2, two fabs with similar processing costs and yield management strategies based on excursion detection have different yield frequency distributions. The two histograms in the figure reflect the yields of the same product manufactured with the same technology. Moreover, neither fab produced wafers with near-zero yield because all low-yielding wafers were detected in-line. However, the one fab produced higher yields than the other because it had instituted a policy of baseline defect density reduction.

 

Figure 2: Histograms of two fabs (A and B) with similar processing costs and yield management strategies show different yield frequency distributions because the higher-yielding fab has instituted baseline defect density reduction.

Wafer Sort Yield Partitioning

At wafer sort, yield loss can be resolved into three categories: Y_rep, or repeating yield loss; Y_S, or systematic yield; and Y_R, or random defect-limited yield.⁴ Each of these components has a different spatial signature, corresponding to different root causes in the fabrication process. Consequently, the three components can be found by analyzing the wafer map of electrical test results.

Y_rep represents yield loss due to reticle defects that occur when there are multiple dies on a reticle. In such cases, the defect is usually a permanent feature of the reticle and the same die fails in each reticle field on the wafer map. Once a repeating defect has been detected, its yield impact can be calculated and the affected die identified and eliminated from the sample before calculating Y_S and Y_R.

Sources of systematic yield loss, Y_S, are failure mechanisms affecting every die in some region of the wafer. Variations in device parameters, such as channel length, threshold voltage, or diffusion resistance, can result in this type of spatial signature. Process parameters affecting device parameters, such as critical dimensions (CDs) and film thicknesses, tend to vary gradually across the wafer. The initial yield ramp associated with bringing a new technology into production focuses primarily on eliminating or fully understanding the systematic sources of yield loss.

Random defect-limited yield,Y_R , is caused by particle-induced defects that in most cases originate in processing equipment and processing materials. They affect dies randomly, with no discernible pattern, but may be clustered in local areas of the wafer. Random yield is strongly linked to the various equipment sets used for different process flows. For this reason, random yield tends to improve much more slowly than systematic yield.

Wafer sort yield is the product of these three components:

The first step in partitioning wafer sort yield is to identify the repeating defects using a pattern recognition algorithm. Then the associated yield loss, Y_rep , can be calculated:

where N is the number of dies per wafer. Subsequently, the remaining yield, Y_tile , is partitioned between Y_S and Y_R:

A tiling, or windowing, algorithm is used to determine Y_S and Y_R based on the wafer map after repeating defects have been identified and removed. In order to resolve these two components, it is necessary to know how yield varies with die size. However, product wafers generally contain only one die size. To overcome this limitation, groups of adjacent dies are defined, whereby the group die area is a multiple of the wafer's die size--that is, 2x, 3x, or 4x larger. A group is considered to have failed if any of the constituent dies fails. Thus, it is possible to determine the yield for the original die size (1x) and for the larger die sizes (2x, 4x, 6x, 9x, etc.). The results are then plotted to see how yield varies with die size. Two different yield models are used to determine random and systematic yield: the Poisson yield model and the negative binomial yield model.

The Poisson Yield Model. Poisson statistics assume uniformly distributed faults across the wafer. In order to partition Y_S and Y_R, assumptions are made about how each component varies with group size. Y_S is assumed to be constant regardless of die size. Because a die must be much smaller than the region affected by the systematic yield loss mechanism for this to be true, group size must be limited. On the other hand, YR varies with the die area A, as in the Poisson equation

where D₀ is the average killer defect density and is the average number of killer defects per die. Thus,

or, taking the natural logarithm of both sides,

Plotting ln Y_tile against A, log Y_S can be determined from the Y-intercept and D₀ from the slope of the curve, as illustrated in Figure 3. The Y-intercept is ­0.073, which means that Y_S = 93%, while the slope of the curve is 0.11, which is the average number of electrical defects per die.

 

Figure 3: The tiling algorithm: table (left) shows yield versus group size based on applying the tiling operation to a wafer sort map; graph (right) shows plot of the same data.

The Negative Binomial Yield Model. In contrast to the Poisson model, negative binomial statistics can model the clustering or the spatial nonuniformity of faults. Clustering can be modeled by fitting the random component of wafer sort yield with the negative binomial yield model. A clustering coefficient, , is used to model spatial nonuniformity. Thus the negative binomial equation is

The drawback to this equation is that it is nonlinear and involves an extra variable; instead of requiring the determination of only Ys and Yo , it also requires the determination of . In addition, it is not given that an overall clustering coefficient is physically meaningful, since the fault density is composed of many different defect sources with different spatial distributions. Because the Poisson model and the negative binomial model are equally useful for modeling small defect densities, determining clustering coefficients is only meaningful for products and lots with low random yields.

Limitations of Wafer Sort Pattern Analysis. After being identified, Y_rep, Y_S, and Y_R can be tracked from lot to lot and wafer to wafer. This ability is extremely useful for diagnosing yield loss mechanisms and for tracking the yield ramp, because increasing levels of Y_S are common during initial yield ramping activities. In addition, D₀ is the electrical defect density. Using D₀and either the Poisson equation or the negative binomial yield equation, Y_R can be predicted for all devices built with the same technology based on die size. Predicting Y_R is linked to determining the yield for products having a mature process, since in mature processes Y_S is known and controllable--that is, it may be equal to one or be optimized based on the trade-off between circuit performance (speed) and yield. However, the accuracy of the yield prediction is limited, because different designs produced by the same technology with the same design rules often have different layout densities. Moreover, if the minimum feature size changes--for example, in the case of a die shrink--wafer sort pattern analysis cannot predict yield at all.

Y_R calculations do not indicate the contributions that various defect sources make to the overall random defect-limited yield. If high metal-1 defect densities are measured in-line, the degree to which yield will be reduced cannot be quantified. Similarly, it is not possible to predict how much yield will improve if defects at the poly deposition stage are removed. Predicting random defect-limited yield more accurately requires the modeling of random yield per layer for specific products.

Random Yield Partitioning

Reducing random yield losses requires the translation of a total killer defect density into product layer or process zone defect densities and ultimately into tool defect densities.

The Sematech Yield Model. Yield modeling is only meaningful if it assesses the root causes of yield losses. Consequently, it must be used to identify and help reduce defects generated by specific tools. In this way, a global yield improvement goal is translated into several goals for which ownership can be assigned. The goal of the Sematech yield model is to set defect budgets for tools by establishing particle-per-wafer-pass (PWP) monitoring data. This goal is achieved by partitioning the electrical defect density, D₀, by process step.

Determining the PWP contribution to D₀ involves several steps.⁵ First, a defect density, d_i , is determined per tool i using in-line scans of monitor wafers. Then each tool is assigned a weight, n_i, corresponding to the number of times the tool is used in the process flow. The total number of defects introduced by the tool set for a given process flow is expressed by the equation

Because PWP defect counts correspond to inspections of blank wafers, many of the defects may be nonkillers. Hence, it is likely that D_PWP>>D₀. To determine the number of killer defects per tool, the defect contribution per tool, D_i, must be scaled by a kill ratio as in the equation:

To refine this model, product wafers, rather than blank monitor wafers, can be measured in-line for defect densities. Defects measured in this way are referred to as in-line process induced defects (PIDs). D₀ is partitioned into process zones, possibly corresponding to layers in a layout. The defect density for zone j, D_PID­j, is optically measured in-line on product wafers that have been processed through the zone. The killer defect density for zone j, D_zone­j, is then estimated using the following kill ratio:

A zone defect density calculated by means of this equation can be used to compute the limited yields per zone with either the Poisson equation or the negative binomial yield equation. Then the defect density per tool, i, used n_ij times in zone j, is computed based on zone defect densities. If the total particle count in zone j is

where

then the killer defects attributed to each tool are computed as follows:

This model has several weaknesses. First, the defect densities per tool, d_i, do not take into account the size and composition of defects. Hence, cosmetic defects, such as film variations, are not differentiated from killer defects, such as large particles. Partitioning is carried out based on the measured defect density at each layer. The model provides no information on the quantity of nuisance defects detected, which vary greatly between layers. Second, the defect densities assigned to a layer of a layout or process zone are related to the cleanliness of the tools used there and do not take into account the density of product layouts and the design rules. Third, the results of using this model depend on the tool and recipe used for in-line wafer scans. As a result of these limitations, tool owners can reduce defect levels without increasing product yield. To improve this model, it is necessary to introduce critical area (CA) analysis.

Critical Area Analysis. CA analysis is used to quantify the sensitivity of a design to defects based on the layout.² Critical area is calculated by defect type and size. Figure 4 shows critical areas for a range of defect sizes for a microprocessor design, which were calculated with the YieldProjector software from HPL (San Jose). The metal bridge faults depicted at left in Figure 4 and the via open faults on the right are the most serious sources of defect yield loss in many processes.

 

Figure 4: Percent of critical area vs. defect size for metal bridging defects (left) and via open faults (right).

The critical areas for intralayer conductor bridging defects are illustrated in Figure 5. In Figure 5a the minimum conductor-to-conductor spacing is 3 µm, and the critical area for 4-µm defects is the total area of the layout, where an electrical fault would result if the area contained the center of a 4-µm-diameter conductive defect. Figure 5b shows critical areas for multiple defect sizes. The critical area increases for larger defect sizes, since a larger defect can cause an electrical fault in more places than a smaller one. In addition to conductor bridge faults, the critical area can be found for conductor breaks or missing metal defects. Additional fault modes include via open defects, or defects which result in enough via resistance to cause a circuit failure, and interlayer conductor bridges, or shorts between layers.

 

a	b
c	d
Figure 5: Critical areas for a range of defect sizes for a microprocessor design: (a) red = area for 4-um bridging defects, blue = metal; (b) red=area for 4-, orange = area for 5-, yellow - area for 6-um defects; (c) geometric critical area calculation step 1, red crosshatch = metal oversized by 2 um; (d) geometric critical area calculation step 2, red = overlap of oversized polygon= 4-um critical area.

There are two ways to calculate critical area for the circuit layout: geometric shifting, or shape shifting, and Monte Carlo.² Geometric critical area extraction involves polygon operations on the layout. This can be illustrated with an intralayer bridging sample generated with YieldProjector for 4-µm bridge defects. First, all polygons are oversized by half the defect diameter, or 2 µm in this example, as illustrated in Figure 5c. Then the area of the overlap area of the oversized regions is calculated, as shown in red in Figure 5d. That is the critical area. Other polygon operations are required for other fault models.

In applying the Monte Carlo critical area extraction method, a large number of defects are placed randomly on the layout in the shape of octagons (to approximate circles). An illustration of this is shown in Figure 6. When dealing with a conductor bridging critical area, it is assumed that these defects are conductive. For each defect, the layout is evaluated by determining whether a netlist change has occurred and whether the defect will result in an electrical fault. The ones that result in electrical faults, or killer defects, are flagged with red markers in Figure 6. To calculate the critical area, the percentage of killer defects for each defect size is multiplied by the total die area:

CA = % of killer defects x total die area

In the example shown in the Figure 6, the percentage of 4-µm killer defects is 3%, the die size is 5.0^­3 cm³, and the critical area is 1.5^­6 cm².

 

Figure 6: Monte Carlo critical area calculation illustrating multiple defect sizes; the defects resulting in electrical faults, or killer defects, are flagged with red markers.

Theoretically, there should be no difference in results between the geometric and Monte Carlo methods, and studies have confirmed this.^6,7 The accuracy of the results can be affected by a number of simulation parameters.⁸ Geometric techniques become prohibitively slow for complex designs, because every polygon must be acted upon individually and scrutinized for its interaction with many other polygons. Therefore, for large dies, the Monte Carlo technique is faster than the geometric technique.⁷ The Monte Carlo simulation time scales linearly with the die area because the number of defects applied must be increased proportionally to maintain accuracy.

Critical Area Yield Modeling. Once critical areas have been calculated, limited yields can be predicted for the relevant process layers. If x is the defect size and L is the layer, then CA_x,L and DD_x,L are the corresponding critical area and defect density. Using the Poisson yield model, the limited yield for defect size x of the layer L is

and the overall limited yield for layer L is

where

is the average number of killer defects per die, sometimes referred to as . DD is the density of physical defects which are potential electrical faults, unlike D₀ above, which represents actual electrical faults. CA, DD, and are illustrated in Figure 7. Critical area increases with defect size, while defect density decreases sharply with increasing defect size. Because of these two trends, usually peaks for defect sizes that are slightly above the minimum space in a layout between two lines. Considering all layers, the overall random defect-limited yield is

This calculation can also be performed with either the negative binomial yield model, as in the equation

with the overall yield

Design for Manufacturability. In addition to being a method of yield prediction, critical area analysis can aid design for manufacturability by improving layouts for better manufacturing yield. Critical areas indicate layout sensitivity to random defects, or yield hot spots. In some cases, a layout can be adjusted to reduce critical areas without affecting the die size or the functionality of the circuit.

 

Figure 7: Critical area, defect density, and the average number of killer defects per die plotted against defect size.

Critical area analysis was used to improve layouts at IBM Microelectronics (Essex Junction, VT), where the metal-1 layout of the PowerPC 604 Processor chip was modified to reduce the critical area.⁹ The modifications were made to instruction and data cache cells, which are repeating structures, to get the maximum leverage from the relayout. When the process engineers compared the efficacy of the old metal-1 mask to the new, modified mask, they discovered that yield with the new mask was 3% better than with the old mask, an impressive, profitable outcome.

Measuring Defect Density for Critical Area Yield Prediction

The yield calculation based on critical area not only requires physical defect densities by layer but also by defect size. How are the defect densities found that are used in the yield calculation? Two approaches have been used to determine the density of potential electrical faults for critical area analysis: optical measurements, with kill ratios for each defect as a function of the defect's composition and size, and electrical defect density monitors.

Optical In-Line Defect Data. Most fabrication facilities routinely detect defect excursions by performing optical in-line inspections at many points in the production process. The tools report defect densities and the size of each defect. These measurements can be used in the calculation of yield based on critical area. However, raw defect densities depend on in-line inspection recipes and may differ substantially from the densities of potential killer defects.¹⁰ Many optically detected defects, such as metal grain boundaries or film variations, do not result in electrical faults because they are cosmetic. Furthermore, optical inspection does not determine the conductivity of defects and whether they can potentially cause bridge faults, break faults, or both.

As automatic defect classification matures, it may become possible to automatically filter out nuisance defects and classify defects according to fault type.¹¹ Then it might be possible to use in-line defect data directly in the critical area yield model. In the meantime, a correlation between in-line defects and electrical results must be established to determine the relationship between optically measured defect densities and potential electrical faults.¹² Moreover, in some fabrication lines defect density is not reported by defect size. In such cases, the size distribution can be approximated by a mathematical model discussed below.

Despite these difficulties, there are excellent fits between a yield predicted with in-line data and critical area analysis and with actual probe yield. Wafer-to-wafer and lot-to-lot yield variation was predicted for SRAMs at STMicroelectronics (Crolles, France).¹³ At that facility critical areas were extracted for both conductor bridge and conductor break defects for active, polysilicon, and metal-1 through metal-5 layers. The resulting yield predictions and actual probe yields for two different products are plotted in Figure 8. The critical area yield model accurately predicted week-to-week yield fluctuations. Week-to-week yield was also modeled accurately at AMD (Sunnyvale, CA).¹⁴ In addition, critical area analysis has been used successfully to accelerate the yield ramp of a leading edge technology.¹⁵

 

Figure 8: Yield predictions from in-line data and critical area analysis compared to actual probe yields for two different products show a high degree of fit.

Electrical Defect Density Monitors. Defect densities for any process layer can be determined with electrical test structures. Examples include comb and serpentine structures that are manufactured as short loops and used for electrical monitors of metal break and bridge defects. When defect densities are measured electrically, all detected defects are killers.

Because defect monitors and product dies have different layouts, defect monitors may be more or less sensitive to defects. In order to apply to the product die the results of using defect monitors, the critical area for both layouts must be determined. The expected number of killer defects per die for a layer, L, where the yield of the defect monitor is Y_DM and the critical area of the defect monitor is CA_x,L ^DM, is computed as: ¹⁶

In this equation, DD_x,L ^norm is a normalized defect size distribution, so that

The size distribution is often approximated using a model in which defect density decreases exponentially with defect size. This model has been widely validated in the industry, both theoretically and experimentally, based on optical and electrical measurements.^2,17­19 The equation takes the form:

where x is the defect size, k^norm is a scale factor that can be found using the equation before last, and n is the size distribution exponent, which is most commonly reported as 3.

Once _L has been found, it can be used in the Poisson yield model in place of

Electrical test structure results are likely to be more accurate than yield models based on optically measured in-line data, because in the former case defect densities are attributed with certainty to a specific electrical fault model, such as conductor breaks or bridges. There are no nuisance defects. However, because scribe line structures are not large enough to detect random defect densities with adequate statistical confidence, special masks and dedicated wafers are required. Different structures are needed to detect each unique type of fault, such as conductor breaks, conductor bridges, open contacts, and defects in active areas. Since measurements from electrical test structures are derived from special test wafers, defect densities do not track actual product lots and wafers. As shown in Figure 9, electrical defect monitors have been used successfully at AMD for partitioning random yield due to shorts in poly and metal layers. Another application is CD targeting.¹⁶

 

Figure 9: Relative yield loss due to conducting particles on seven layers of a microprocessor product.

Conclusion

This article has surveyed techniques for partitioning yield into random and systematic components and for further partitioning the random defect-limited yield component to reflect individual defect sources in the process. By partitioning yield into components, ownership can be assigned to defect reduction efforts and, consequently, yield enhancement efforts can be made more effective.

The Sematech model for partitioning random defect limited yield was introduced. It was shown how the use of CA analysis can improve this model so that defect reduction work can focus on the most critical defects. Focusing on the most critical defects is the first of three primary applications of CA analysis. This analysis also enables yield modeling based on layout and process defect densities so that yield fluctuations from in-line defect measurements can be predicted. Yield predictions enable chipmakers to carry out factory-capacity planning, financial projections, and feasibility studies for new projects. For example, companies deciding between fabrication facilities or foundries can rely on the defect densities at each facility to predict the random defect-limited yield for each product, thus promoting the efficient allocation of resources. Finally, CA analysis can foster design for manufacturability efforts so that circuit layouts can be altered to reduce their sensitivity to random defects. Such efforts can lead to dramatic improvements in yield and profitability with relatively modest input.

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Julie Segal, PhD, is responsible for developing software tools for yield modeling, yield improvement, and design for manufacturability at HPL (San Jose). She has seven years of semiconductor experience at Xicor and Cypress Semiconductor. Segal has published papers on critical area analysis and yield modeling. She received a BA in physics from the University of California, Berkeley, and an MS and PhD in electrical engineering from Stanford University in Palo Alto, CA. (Segal can be reached at 408/501-9257 or julies@hpl.com.)

Linda Milor, PhD, is the device engineering manager in the product engineering department of the submicron development center at Advanced Micro Devices (AMD) in Sunnyvale, CA, where she has been since 1995. Before joining AMD, she was an assistant professor of electrical engineering at the University of Maryland (College Park). Milor has published in the areas of yield modeling, yield enhancement, circuit performance prediction, analog integrated circuits testing, and statistical modeling. She received a PhD in electrical engineering from the University of California, Berkeley. (Milor can be reached at 800/522-6245 or linda.milor@amd.com.)

Yeng-kaung Peng, PhD, is the director of yield, product, and test engineering in the submicron development center at AMD. In 1983 he joined Monolithic Memory, which later merged with AMD, and has held various technical and managerial positions ever since. From 1981 to 1983, Peng was a member of the technical staff of Nitron. He received a PhD in materials science from the University of Nebraska in Lincoln. (Peng can be reached at 800/522-6245 or yengkaung. peng@amd.com.)